About the configuration register and read ID I have tried, no problem on timing, can be configured and read
Void SSD2828_Init (void)
{
SSD2828_QSPI_Init ();
//Packet Write Configuration
Xb8 SSD2828_Write_REG (0, 0 x0000);//VC (Virtual ChannelID) Control Register
Xb9 SSD2828_Write_REG (0, 0 x0000);//PLL Disable

//PLL Configure
//FR: bit15 ~ 14
//00? 62.5 & lt; The OUT f & lt; 125
//01? 126 & lt; The OUT f & lt; 250
//10? 251 & lt; The OUT f & lt; 500
//11? 501 & lt; The OUT f & lt; 1000
Xba SSD2828_Write_REG (0, 0 xc050);//Fout=0 x14 Fin */1=10 m * 80/1=800 m
X0009 XBB SSD2828_Write_REG (0, 0);//LP (Low Power) Clock Fout/=10/8=10 m
Xb9 SSD2828_Write_REG (0, 0 x0001);//PLL ENABLE
HAL_Delay (100);

//RGB Input Interface Control
SSD2828_Write_REG (0 xb1, (SSD2828_VSYNC & lt; <8) + SSD2828_HSYNC);
SSD2828_Write_REG (0 sets, (SSD2828_VBP & lt; <8) + SSD2828_HBP);
SSD2828_Write_REG (0 xb2, (SSD2828_VFP & lt; <8) + SSD2828_HFP);
SSD2828_Write_REG (0 xb4, SSD2828_WIDTH);
SSD2828_Write_REG (0 xb5, SSD2828_HEIGHT);
Xb6 SSD2828_Write_REG (0, 0 x0003);//HS, VS, PCLK=0, Bit [1:0]==24 BPP

//Delay Timeing
//SSD2828_Write_REG (x0001 xc4 0, 0);//Enable BTA
Xc9 SSD2828_Write_REG (0, 0 x2302);//p1: HS - Data - zero p2: HS - Data - prepare - & gt; Issue 8031
HAL_Delay (5);
Xca SSD2828_Write_REG (0, 0 x2302);
XCB SSD2828_Write_REG (0, 0 x0510);
SSD2828_Write_REG (0 XCC, 0 x1005);//HS CLK Trail
HAL_Delay (5);
Xd0 SSD2828_Write_REG (0, 0 x0000);//HS TX Timer=0,?????=0 x0010

//Configure MIPI Lane
//lane mode 00-1
//01-2 lane mode
//10-3 lane mode
//11-4 lane mode
Xde SSD2828_Write_REG (0, 0 x0003);//2 Data Lane, 11 10=3=4 Lane Lane 01 00=1=2 Lane Lane
Xd6 SSD2828_Write_REG (0, 0 x0005);//Bit [when] : Send X (now=1) Packet in Blanking Period, Bit [0] : 1=R.G.B/0=B.G.R
Xb7 SSD2828_Write_REG (0, 0 x024b);//0 x024b choose TX_CLK as MIPI clock, 0 x026b choose RGB PCLK as MIPI clock
HAL_Delay (100);

}