I understand that for J-format instructions, the 32-bit instruction is split into a 6-bit opcode and a 26-bit target address. By realising that the last 2 bits will always be 0 since jumps can only jump to word-aligned addresses, we are able to specify 28 out of the 32-bit address indirectly.
We are then told that to get the other 4 bits, MIPS chooses to take the 4 most significant bit from PC 4. My question is that what if PC 4 is so far ahead/behind, such that its 4 most significant bits are different from the 4 most significant bits of our intended destination, does that mean that we're unable to reach our intended destination?
CodePudding user response：
does that mean that we're unable to reach our intended destination?
Yes, you cannot reach all 32-bits of the address space with a J-type instruction. Effectively, a statically linked code segment using j jumps is limited to 228 bytes in size, if you want to be able to jump from the beginning to the end or vice versa.
If you really want to reach anywhere in the address space, you'll need a jump register, jr (or jalr) and have the appropriate address in a register, which could be assembled using lui/addi pair, or loaded from data, as could be the case when using a function pointer. For a 32-bit machine, these approaches can both reach any location in the address space.
Note that dynamically loaded libraries are typically each separately linked chunks of code, and inter-DLL invocations could be using jr in some way.
Also, to add to the discussion, RISC V does a much better job in this regard, having eliminated this approach to having 16 large code segments; plus, they added another counterpart to lui, namely auipc — that has the same usage as lui but computes a pc-relative value that can be used instead to make code more position independent; while the jalr instruction has been upgraded to have an immediate, so can be used in a 2 instruction sequence auipc; jalr. Further, the RISC V toolchain supports linker relaxation, a complex mechanism that allows the linker to shorten code sequences at link time when they would reach with fewer instructions.