Question similar to here, but for my use case, I'd like to place inside the makefile.
#!/bin/bash
# Example:
# make run TEST_CASE="testbench.sv"
# make clean
compile:
vcs $(TEST_CASE) -sverilog;
run: compile
./simv
uvm_compile:
vcs $(TEST_CASE) -sverilog;
clean:
shopt -s extglob;
rm -v !(*.sv|*svh|"makefile");
The problem exist in make clean, and I got the following result:
ycliao@localhost:[~/workspace/i2c_vip/uvm_practice]: make clean
shopt -s extglob;
rm -v !(*.sv|*svh|"makefile");
/bin/sh: -c: line 0: syntax error near unexpected token `('
/bin/sh: -c: line 0: `rm -v !(*.sv|*svh|"makefile");'
make: *** [clean] Error 1
CodePudding user response:
As I understand makefiles, every line is executed in a separate shell. So you need to add a line continuation to concatenate the commands so that they execute in the same shell:
SHELL = /bin/bash
# ...
clean:
shopt -s extglob; \
rm -v !(*.sv|*svh|"makefile");
This is demonstrated in Example makefiles on the wikipedia Make page.
CodePudding user response:
ycliao@localhost:[~/workspace/i2c_vip/uvm_practice]: make clean
shopt -s extglob; \
rm -v !(*.sv|*svh|"makefile");
/bin/bash: -c: line 1: syntax error near unexpected token `('
/bin/bash: -c: line 1: `rm -v !(*.sv|*svh|"makefile");'
make: *** [clean] Error 1