Makefile: Compile C Files recursively-CodePudding

I am new to makefiles and tried reading resources on the internet to solve my problem, yet I am unable to find a solution.

Basically I am working on a project which contains C and Cuda files. Since I like to keep my things structured, I usually use a nested folder structure like this:

 |- bin
 |- build
 |  |- cc
 |  |- cu
 |- src
 |- makefile
 |- main.cpp

My current Makefile looks like this:


CC       = g  
NVCC     = nvcc
CC_SRC   = $(wildcard *.cpp */*.cpp */*/*.cpp */*/*/*.cpp)
CU_SRC   = $(wildcard *.cu */*.cu */*/*.cu */*/*/*.cu)

CC_LIBS  = -pthread -Wl,--whole-archive -lpthread -Wl,--no-whole-archive

ROOT     = ./
FOLDER   = $(ROOT)bin/
OBJECTS  = $(ROOT)build/
CC_OBJ   = $(OBJECTS)cc/
CU_OBJ   = $(OBJECTS)cu/
NAME     = Test
EXE      = $(ROOT)$(FOLDER)$(NAME)

NVCC_FLAGS =
CC_FLAGS =

## Compile ##
run:build

build: $(EXE)

$(CC_SRC):
    @echo compiling
    $(CC) $(CC_FLAGS) -c $< -o $a

$(EXE) : $(CC_SRC)
    @echo test 123

Initially I wanted to compile all C files to the build/cc files. Similarly my .cu files should be compiled into the build/cu folder.

Initially I made a wildcard which catches all the c files:

CC_SRC   = $(wildcard *.cpp */*.cpp */*/*.cpp */*/*/*.cpp)
CU_SRC   = $(wildcard *.cu */*.cu */*/*.cu */*/*/*.cu)

But for some reason the according rule is not being executed. I am happy if someone could help me here.

Greetings Finn

CodePudding user response：

This rule doesn't make sense:

$(CC_SRC):
        @echo compiling
        $(CC) $(CC_FLAGS) -c $< -o $a

(I assume you mean $@ here not $a). This rule says that the way to create each of the source files is by compiling them. But, make doesn't need to build the source files: they already exist. So it never invokes your rule.

You need your target to be the file you want to create, not the file that already exists. The file you want to create is the object file, not the source file. Then the prerequisite is the file that already exists. So for a compilation you want a pattern rule, like this:

$(CC_OBJ)%.o : %.cpp
        @echo compiling
        @mkdir -p $(@D)
        $(CC) $(CC_FLAGS) -c $< -o $@

Then you want your target to depend on the object files, not the source files, like this:

$(EXE) : $(CC_SRC:%.cpp=$(CC_OBJ)%.o)
        @echo test 123

CodePudding user response：

I recommend migrating your project to CMake (https://cmake.org/cmake/help/latest/), in particular if your project is not too big yet.

Makefiles can be really a pain; CMake can ease matters considerably.