I am studying about Linux Context Switch on the ARMv8
Below is the codes
ENTRY(cpu_switch_to) mov x10, #THREAD_CPU_CONTEXT add x8, x0, x10 mov x9, sp stp x19, x20, [x8], #16 // store callee-saved registers stp x21, x22, [x8], #16 stp x23, x24, [x8], #16 stp x25, x26, [x8], #16 stp x27, x28, [x8], #16 stp x29, x9, [x8], #16 str lr, [x8] add x8, x1, x10 ldp x19, x20, [x8], #16 // restore callee-saved registers ldp x21, x22, [x8], #16 ldp x23, x24, [x8], #16 ldp x25, x26, [x8], #16 ldp x27, x28, [x8], #16 ldp x29, x9, [x8], #16 ldr lr, [x8] mov sp, x9 msr sp_el0, x1 ret ENDPROC(cpu_switch_to)
Question 1: Just Callee Registers (X19 ~ X29, Link Register, SP) are enough for Context Switch. Why the rest of registers (X0 ~ X18) are not involved in Strong and Restoring of context using stack? The task context is kind of sequence of function. So, Callee Registers are enough for context switch?
Question 2: PC (Program Counter) Register is not involved in Strong and Restoring of context using stack. This is because the pc is restored when this callee function has return? At that time link register is copied into PC?
Question 3: PSTATE Register is not involved in Strong and Restoring of context using stack. Is there any reason to do like this? I think that task context should contain PSTATE Register.
If somebody answers my question. I would be grateful.
CodePudding user response：
It isn't the case that only some registers are saved in a context switch. That's because a context switch may occur for any number of reasons, including a page fault, and obviously it would be unsuitable if any time you accessed memory some of your registers could be lost.
Typically the registers and other state are stored on the stack upon entry to the interrupt routine and restored on exit. This is a different piece of code from what you've mentioned, which is an internal thread switch. Typically the functions involved in task switching are called something like irq_handler because a context switch is often caused by an interrupt, and on ARM64, I believe the code to return to userspace is called something like asm_exit_to_user_mode.
You can read the ARMv8 documentation on context switches to learn more.
CodePudding user response：
First Thanks for your answer. But I think your focusing is different from what I want
I have studied about exception handler and irq handler written in assembly codes. I don’t fully understand those codes. But my understanding is like below
When the ARM Exception including interrupt occurs, the exception handler codes execute like “kernel_entry” which saves CPU Context of current task(thread) using current task’s stack with C structure of pt_regs. That structure includes All Registers of X0 ~ X30, SP, PC, PSTATE register. And then execute the exception handler which is sometimes irq handler. After that handler “kernel_exit” codes execute which restoring CPU Context that is previously saved.
That IRQ handler which is sometimes timer interrupt decides whether it is necessary to reschedule (context switch). If it is needed. A function of schedule should be called
schedule
context_switch
3.1 swtich_mm … cpu_do_switch_mm about Address Mapping
3.2 switch_to … cpu_switch_to about cpu context
What I was talking about is about CPU Context. Especially about assembly codes of “cpu_switch_to”. In the previous ARM codes, I remember that they store all of CPU registers including SPSR and restore all. Anyway the context of CPU register should be changed in case of context-switching. My question is that CPU context does not have registers of X0 ~ X18, PC, PSTATE registers. Why?