Tying to do frequency scaling of 50 MHz signal to 1MHz with below code. "endmodule" error-CodePudding

module PWM_Gen(

input clk,             // Clock input
input [7:0]DUTY_CYCLE, // Input Duty Cycle
output PWM_OUT         // Output PWM
);

reg [7:0]counter_out; // 8-bit counter

always @(posedge clk)   
begin
   if (DUTY_CYCLE > counter_out)
   PWM_OUT = 1;
   else
   PWM_OUT = 0;
end
counter counter_inst(   
.clk(clk),
.counter_out(counter_out)
)

endmodule

error is -

Error (10170): Verilog HDL syntax error at PWM_Gen.v(51) near text: "endmodule"; expecting ";".

Q2. I didnt understand how clock input is realted to duty cycle & how i implement it in code? Q3.I didn't understand how i will get output of 1MHz?

CodePudding user response：

It's a typo, you need a ; after the counter_inst instantiation

CodePudding user response：

Assuming your clock is 50MHz, you just need to set your counter_out value to 25, so that PWM_OUT would be 1MHz with 50% duty.