When testing with a testbench in VHDL we map the I/O from the design we are testing to the I/O of the test bench.

For me, it would make sense to give the input of our design some generated values from the testbench and then observe the output from the design and check if it matches what we expect. (Like in unit testing e.g.)

But when defining the architecture of the testbench:

architecture behavior of tb is 
  
  signal tb_input : std_logic := '0'; 
  signal tb_output: std_logic := '0';

  -- Component decl. for the Unit under Test (UUT)
  component design_to_test is 
   port (
      input : in std_logic; 
      output: out std_logic);
  end component design_to_test; 

begin 
   -- Here we initiate the UUT
   UUT : design_to_test
      port map ( 
        input => tb_input
        -- this is what I don't understand. Why are we 
           giving the input of our design to the testbench? 
        output => tb_output
        -- this makes sense to me as we have to observe the 
           the output of our design. 
       ); 
       -- main testing 
end behavior; 

So essentially the part I don't understand is how we use the input of the testbench. Why aren't we defining some input and then giving it to the design to evaluate?

CodePudding user response：

Actually you need to stimulate the input of your UUT.

Currently your test bench is not complete.

Add some sequence to assign different values to tb_input.

And then add some checks that tb_output carries the expected values.

The port map just tells the simulator (or the synthesizer if you are synthesizing) which ports are connected to what signals of the outer level.

So input => tb_input does not mean that the data flows from input to tb_input. It says that the port input has to be connected to the signal tb_input. The data directions is derived from in and out keywords.

Look at it as the IC socket and the connected nets, which are the signals of the outer level, and the IC plugged into the socket and its pins, which are the ports of your component.