Why does make not see the rule?-CodePudding

I have a very simple Makefile and it gets stuck on No rule to make target '%.o', needed by 'output.exe'.

I only have 1 c file called main.c and it is in the same directory as my Makefile

My Makefile looks like this:

COMPILER_FLAGS = -g -Wall
COMPILER = gcc

all: output.exe

output.exe: %.o
    $(COMPILER) $(COMPILER_FLAGS) %.o -o $@

%.o: %.c
    $(COMPILER) $(COMPILER_FLAGS) -c @< -o $@

clean:
    rm *.o output.exe

I have no clue why it doesn't see the rule. Can anyone tell me what the problem is?

CodePudding user response：

This is not doing what you think it's doing:

output.exe: %.o

That is not a pattern rule. A pattern rule must have a pattern character (%) in the target of the rule. The pattern character may or may not be present in the prerequisites but it MUST appear in the target. Otherwise, it's just a normal explicit rule.

Here you have told make that the target output.exe depends on a prerequisite file literally named %.o, and of course make has no idea how to build a file named %.o because you don't have a file named %.c or %.cpp or whatever.

CodePudding user response：

Make does see you rule. Actually you have to tell make which source files must be compiled to objects:

SRC = main.c
OBJ = $(SRC:%.c:%.o)

...

output.exe: $(OBJ)