Makefile: Regexp pattern for prerequisite file(s)-CodePudding

I am trying to write a make recipe for a cross-compilation of an asm file. The thing is, that I want to use a regex as a makefile prerequisite for the output target because these assembly files are generated in a somewhat automatic way.

So, their names follow the following pattern:

1_mps.S # i want this to be compiled into 1_mps.elf
2_mps.S # i want this to be compiled into 2_mps.elf
3_mps.S # i want this to be compiled into 3_mps.elf

and so on...

I am trying to find the appropriate handling of this somewhat dynamic rule definition in the Makefile documentation but I am a little bit lost and I need some assistance.

So, how can I define a prerequisite for that and also name the output file like that?

So far, I have tried using wildcards and % patterns but with no success.

For example:

out.elf : %_mps.S, vectors.S, syscalls.c
      ... gcc cross-compiler invocation here...

out.elf : *_mps.S, vectors.S, syscalls.c
      ... gcc cross-compiler invocation here...

Of course, both of these examples are not working but also, they do not yield the respective outfiles. For example even if they would work they would produce the name out.elf in all cases (i.e., for every of the n_mps.S input files)

My (not-working) attempt:

RISCV_EXE_PREFIX         = $(RISCV)/bin/riscv32-unknown-elf-

all: %_mps.hex

$_mps.elf: %_mps.o syscalls.c vectors.S
    $(RISCV_EXE_PREFIX)gcc -o $@ \
        -T link.ld \
        -static \
        $^  \
        -I $(RISCV)/riscv32-unknown-elf/include \
        -L $(RISCV)/riscv32-unknown-elf/lib 

%_mps.o : %_mps.S
    $(RISCV_EXE_PREFIX)gcc -march=rv32imcxpulpv2 -c -w -Os -g -nostdlib \
    -I $(RISCV)/riscv32-unknown-elf/include \
    -L $(RISCV)/riscv32-unknown-elf/lib \
    -lc -lm -lgcc

%_mps.hex: %_mps.elf
    $(RISCV_EXE_PREFIX)objcopy --output-target=verilog $< $@

.PHONY:
clean:
    rm -rf $(PROGRAM_NAME).elf $(PROGRAM_NAME).hex

make: *** No rule to make target '%_mps.hex', needed by 'all'. Stop.

CodePudding user response：

You may like to use pattern rules to compile your source files into object files first and then link object files into ELF object:

all : 1_mps.elf 2_mps.elf 3_mps.elf

%_mps.S :
    # Create .S
    touch $@

%_mps.o : %_mps.S
    # Compile .S into .o
    echo "$^" > $@

%_mps.elf : %_mps.o
    # Link .o into .elf
    echo "$^" > $@

.PHONY: all
.PRECIOUS: %_mps.S %_mps.o # Needed because it makes source files with touch.

Output:

$ make
# Create .S
touch 1_mps.S
# Compile .S into .o
echo "1_mps.S" > 1_mps.o
# Link .o into .elf
echo "1_mps.o" > 1_mps.elf
# Create .S
touch 2_mps.S
# Compile .S into .o
echo "2_mps.S" > 2_mps.o
# Link .o into .elf
echo "2_mps.o" > 2_mps.elf
# Create .S
touch 3_mps.S
# Compile .S into .o
echo "3_mps.S" > 3_mps.o
# Link .o into .elf
echo "3_mps.o" > 3_mps.elf

$ make
make: Nothing to be done for 'all'.