A total of 16 address thread CPU, 8 data line, and MREQ (low level) effectively to fetch control signal, R/W for the read/write command signal (high level of reading, low level of writing), the existing memory chips: ROM (2 kx8, 4 kx4, 8 kx8), RAM (1 kx4, 2 kx8, 4 kx8) and 74138 decoder and other gate (gate)
Try to choose appropriate contact plate, from the above specification of the CPU and memory chips connection diagram, request the following
(1) minimum 4 k address for the system application area, 4096-16383 address range for the user program area
(2) points out that the use of memory chip type and quantity,
(3) detailed draw a piece of logic,