The macro safe_svcmode_maskall in arch/arm/kernel/head.S is defined in arch/arm/include/assembler.h,which is

.macro safe_svcmode_maskall reg:req
#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
    mrs \reg , cpsr
    eor \reg, \reg, #HYP_MODE
    tst \reg, #MODE_MASK
    bic \reg , \reg , #MODE_MASK
    ......

I found there is a HYP_MODE and learned through some brief introduction that it is hypervisor mode.But I failed to get its detailed introduction in armv7 architecture reference manual.Actually I did't find the word in the manual.It can't be equal to svc mode,because svc mode is also mentioned in the context of the code.

Besides,I noted that there is ':req' after the 'reg' which is a parameter.I've learned ':req' means the 'reg' can't be empty.But I can't find the definition of ':req' in gnu arm assembler manual.

It may be simple question.But I want to learn how to find these answers in official manual.(I still believe answers are in these manual.Maybe I did't choose the corresponding version)

CodePudding user response：

Last question

But I can't find the definition of ':req' in gnu arm assembler manual.

From the GNU assembler manual,

You can qualify the macro argument to indicate whether all invocations must specify a non-blank value (through ‘:req’), or whether it takes all of the remaining arguments (through ‘:vararg’). You can supply a default value for any macro argument by following the name with ‘=deflt’.

And the example,

.macro m p1:req, p2=0, p3:vararg

Begin the definition of a macro called m, with at least three arguments. The first argument must always have a value specified, but not the second, which instead has a default value. The third formal will get assigned all remaining arguments specified at invocation time.

First question

I found there is a HYP_MODE and learned through some brief introduction that it is hypervisor mode.But I failed to get its detailed introduction in armv7 architecture reference manual.Actually I did't find the word in the manual.It can't be equal to svc mode,because svc mode is also mentioned in the context of the code.

There is a hypervisor mode for ARMV7A (not ARM7M) on some CPUs, but not all.

See: Hypervisor mode and ARM Virtualization extensions.

If the extension does not exist, it is still fine to alter this bit on ARM7A.