Identifier must be declared with a port mode error in verilog-CodePudding

//3.v
module and3(x,y,z,w1,s);

input x,y,z;
wire w1;
output s;

assign w1=y&z;
assign s=w1|x;

endmodule

I got error here. "Identifier must be declared with a port mode error:w1". I searched similar errors but I think I declared it right. Or does my testbench wrong?

`timescale 1ns/1ns
module testbench;
reg x,y,z;
wire w1,s;

and3 and3(x,y,z,w1,s);

initial
begin
#250;x=0;y=0;z=0;
#250;x=0;y=0;z=1;
#250;x=0;y=1;z=0;
#250;x=0;y=1;z=1;
#250;x=1;y=0;z=0;
#250;x=1;y=0;z=1;
#250;x=1;y=1;z=0;
#250;x=1;y=1;z=1;
end

endmodule

How should I correct ?

CodePudding user response：

Its telling you it wants the direction.

Like this:

module and3(x,y,z,w1,s);

input x,y,z;
output s,w1;

assign w1=y&z;
assign s=w1|x;

endmodule

Port defaults are confusing, better to specify and make the design intent clear. Don't count on the reader of your code knowing all the default rules for type, kind, direction etc.

See
https://www.edaboard.com/threads/default-type-of-a-systemverilog-port.390303/

Particularly the comments by dave_59