I wanted to create a C program to create several different executable binaries from the same Makefile with different names.
but as everytime I run "make" of a pretty large program, they have this bunch logs output... and if i made several of this the terminal would be so "dirty"
So the question, is it actually okay to run "make" in background, so i don't have to see those log? is it a good idea? or does this actually has no relation with putting it to the background or so?
and if yes, how can i do so?
For the program it's more or less like below, where tmp2 is array of the binaries name
for (int j = 0; tmp2[j] != NULL; j )
{
printf("-> %s\n", tmp2[j]);
char command[128] = "";
sprintf(command, "make -C %s TARGET=%s all", "file/path/", tmp2[j]);
system(command);
}
and I tried to look up for running linux command in background like adding & at the end of the command, but it still shows the log
text.c:442:3: warning: blablabla
gcc -W -Wall -Wextra -c -g -Os -I. test1.c
gcc -W -Wall -Wextra -c -g -Os -I. test2.c
gcc -g -o STEM_ECS2_SERVICE_3 main.o json.o config.o debug.o -lnsl -lm -ldl -lc -lmysqlclient -lm
/bin/mv *.o ./object
the log is sth like above, its the simplified version, it's just all the stuff from -Wall and the actual command like gcc
stuff
So is there actually any way to not see the "make" log?
EDIT
for the make file
include ../../Make.cf
OBJ_DIR = ./object
CFLAGS = -g -Os $(INCDIR) $(MYSQLINC) -I./include -export-dynamic
LDFLAGS = $(SYSNLIB) $(SYSLIB) $(MYSQLLIB) $(THREADLIB) -L$(LIBDIR) \
-lmysqlclient -lm
C_OBJECTS = main.o \
json.o \
ecs_config.o \
ecs_debug.o \
######### define target #########
all: $(TARGET)
main.o: main.c
$(CC) -W -Wall -Wextra -c $(CFLAGS) $(DEFINES) main.c
json.o: json.c
$(CC) -W -Wall -Wextra -c $(CFLAGS) $(DEFINES) json.c
config.o: config.c
$(CC) -W -Wall -Wextra -c $(CFLAGS) $(DEFINES) config.c
debug.o: debug.c
$(CC) -W -Wall -Wextra -c $(CFLAGS) $(DEFINES) debug.c
$(TARGET): $(C_OBJECTS)
$(CC) $(CFLAGS) $(DEFINES) -std=gnu99 -o $(TARGET) $(C_OBJECTS) $(LDFLAGS)
$(MV) *.o $(OBJ_DIR)
touch:
$(TOUCH) *.c
clean:
$(RM) $(OBJ_DIR)/*.o
rm -f *.o core $(TARGET)
cp:
cp -f $(TARGET) $(BINDIR)/$(TARGET)
so this make file is actually made by someone else from the group, and I cant really show the exact path to stuff, but hope this help
CodePudding user response:
First of all, running the same make/makefile in parallel with different instances of make can result in race conditions -- so no, it's not a good idea. (eg. if instance 1 of make was trying to access a dependency that instance 2 was in the process of updating, you could end up with corrupt data)
That being said, you can get around that by just using a single instance of make as so:
make -j targ1 targ2 targ3
This will build targ1
, targ2
, and targ3
, will build dependencies only once for all targets, and will build everything in the correct order etc.
I'm not clear why you would want to call this from a c file rather than just use the command line, but if there is a reason for this, you would want it to look something like:
char command[1024] = "";
char *eo_command = command sizeof(command);
char *ptr = command;
ptr = snprintf(command, sizeof(command) "make -C %s", "file/path/");
// add some checks to ptr here...
for (int j = 0; tmp2[j] != NULL; j ) {
ptr = snprintf(ptr, eo_command-ptr, " %s", tmp2[j]);
// add some checks to ptr here...
}
system(command);
If you don't want to see the output, you can pipe the output to /dev/null
. Also, if you want it to build faster, you can pass a -j
flag to the make command line which will allow it to build multiple targets in parallel.
CodePudding user response:
it is possible to call the make
command with a &
at the end, so the process spawns in the background, and you get the PID.
Something like that:
make -SOME_FLAGS &