Can we use conditions in ifdef MACROS in C or SystemVerilog?-CodePudding

I want something like that

    `ifdef N_O > N_I
        `define GREATER 1
    `else
        `define LESSER 1
    `endif

But cannot do. Any solution or reading?

I tried hard to do this but could not do it.

CodePudding user response：

#ifdef only tests if a macro is defined, regardless of the value it represents.

If you want to compare their values, you need to use #if

#if N_O > N_I
    
#endif

In Verilog, you can only do it this way:

`ifdef N_O
    `ifdef N_I
        if(N_O > N_I)
            ...
    `endif
`endif

CodePudding user response：

Verilog does not provide such a facility. There is only one action possible with text macros: checking for their existence. Therefore there are `ifdef, `ifndef, and `elsif. All accept only a single argument which is the name of a text macro.

In many cases, however, this shortage of functionality could be augmented by using generate verilog features. Use of this feature is preferable because verilog controls syntax and scoping of declarations.

The following is an example of using generated functionality:

module mod #(parameter N_0=1, parameter N_1=2)(input logic in1, in2, output logic out);
    if (N_1 > N_2) begin
         always_comb
             out = in1;
    end
    else begin
         always_comb 
             out  = in2;
    end
endmoudle

This was a made up example to demonstrate the feature, which could be implemented without 'generate' blocks:

    alwas_comb begin
        if (N_1 > N_2) out = in1;
        else out = in2;
    end

However, the generate constructs cannot solve all the problem, therefore mixing of text macros and generate blocks is often needed.