OpenOCD debugging Stops after STM32 Sleep-CodePudding

When debugging the STM32 with OpenOCD and GDB, OpenOCD does not continue to debug when the MCU wakes up from STOP mode.

I have the following code which sleeps the MCU for 10 seconds and then wakes it up:

uint32_t seconds = 10;
uint32_t counter = (uint32_t)(seconds * 1000) / 0.488;
HAL_RTCEx_SetWakeUpTimer_IT(&hrtc, counter,
                              RTC_WAKEUPCLOCK_RTCCLK_DIV16);
  HAL_SuspendTick();
  HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI);
  SystemClock_Config();
  HAL_ResumeTick();
  do_stuff():

When I use the STM32CubeIDE with ST's Programmer, it works as expected. The debugging process continues to the next line after the MCU wakes up.

With OpenOCD and GDB and stays stuck at

Continuing.
halted: PC: 0x080010f0

How can I make it behave similar to the ST debugger, where it continues debugging after sleep?

I use the following line to start the OpenOCD session:

 openocd -f interface/stlink-v2.cfg -f target/stm32f4x.cfg

CodePudding user response：

You have to enable debugger STOP-mode support. Quote from the reference manual:

The core does not allow FCLK or HCLK to be turned off during a debug session. As these are required for the debugger connection, during a debug, they must remain active. The MCU integrates special means to allow the user to debug software in low-power modes. For this, the debugger host must first set some debug configuration registers to change the low-power mode behavior:

• In Sleep mode, DBG_SLEEP bit of DBGMCU_CR register must be previously set by the debugger. This will feed HCLK with the same clock that is provided to FCLK (system clock previously configured by the software).

• In Stop mode, the bit DBG_STOP must be previously set by the debugger. This will enable the internal RC oscillator clock to feed FCLK and HCLK in STOP mode

From description of the DBGMCU_CR register.

Bit 1 DBG_STOP: Debug Stop mode

0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all clocks (including HCLK and FCLK). When exiting from STOP mode, the clock configuration is identical to the one after RESET (CPU clocked by the 8 MHz internal RC oscillator (HSI)). Consequently, the software must reprogram the clock controller to enable the PLL, the Xtal, etc.

1: (FCLK=On, HCLK=On) In this case, when entering STOP mode, FCLK and HCLK are provided by the internal RC oscillator which remains active in STOP mode. When exiting STOP mode, the software must reprogram the clock controller to enable the PLL, the Xtal, etc. (in the same way it would do in case of DBG_STOP=0)

I think HAL_DBGMCU_EnableDBGStopMode() function is resposible for this register. But you may need to check the exact library version you using.

Probably STProgrammer modifies this bit silently.