No rule to make target - makefile-CodePudding

This is my makefile:

CC=gcc
CFLAGS=-c -O2 -Wall -fcommon -I./INC

#umiestnenie zdrojakov kniznice
SRC_LIB_DIR=SRC_LIB

#automateicke generovanie zdrojakov kniznice
SRC_LIB := $(wildcard $(SRC_LIB_DIR)/*.c)
OBJ_LIB=$(SRC_LIB:.c=.o)

#meno vykonatelneho programu
EXECUTABLE=test_rx test_tx
#vymenovanie zdrojakov aplikacie
SRC_EXE=demo_rx.c demo_tx.c
OBJ_EXE=$(SRC_EXE:.c=.o)

all: $(SRC_EXE) $(SRC_LIB) $(EXECUTABLE)

%: .o 
    $(CC) -o $@ $  

.c.o:
    $(CC) $(CFLAGS) $< -o $@

clean:
    rm -f $(EXECUTABLE).exe *.o *.a SRC_LIB/*.o

The folder looks like this:

example_RS232
      |__INC (rs232.h, example_modified_rs232.h)
      |__SRC_LIB (rs232.c, example_modified_rs232.c)
      |__demo_rx.c
      |__demo_tx.c
      |__makefile

Compiled in C in mingw on Windows.I'm trying to compile the demo_rx.c and demo_tx.c files into the test_rx and test_tx executables. I get an error when compiling:

make: *** No rule to make target 'test_tx', needed by 'all'.  Stop.

I don't know why I have got this error.

CodePudding user response：

Basically, you should try to never use "match-anything" rules. A match-anything rule is a rule where the target is just %. That rule can (as the name implies) match ANY target. It could match foo, foo.o, foo.c, foo.h, or any other thing anywhere in the makefile.

This makes these types of rules REALLY inefficient as make has to consider this rule, and the prerequisites, etc. for every target. It's also easy to get into loops this way.

Because of this, make installs a whole bunch of extra restrictions on match-anything rules that don't exist for other pattern rules. You can read all about this in the GNU make manual discussion but the best take-away is, "don't use them".

I recommend you replace this with a static pattern rule:

$(EXECUTABLE) : %: .o 
        $(CC) -o $@ $