A makefile can handle multiple output-CodePudding

For example I have something like:

SRC = a.cpp b.cpp
INC = somedir/inc anotherdir/inc
OBJ = a.o b.o

How can I have the makefile build every obj automatically in one rule instead of one each rule

CodePudding user response：

Assuming GNU make, there will be an implicit rule that make every object file dependent on the corresponding source file. This implicit rule will build the object file from the source file.

Unless you need to specify dependencies on header files, a very simple makefile could look just like this:

OBJS = a.o b.o

myexe: ${OBJS}

That's it. It will make sure that the object files are build before linking them into the myexe program.

To add new "source" files, you can just add the corresponding object file to the OBJS variable. For example if you also want to build with c.cpp then change it to:

OBJS = a.o b.o c.o

Leave the myexe target as it is.

CodePudding user response：

Take a look at https://www.gnu.org/software/make/manual/html_node/Pattern-Examples.html#Pattern-Examples

%.o : %.cpp
    $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@

See comment from "some programmer dude" ... he is absolutly right ...