Assigning the entirety of a 2D packed array to a 1D packed array with the same number of elements-CodePudding

I have the following signals:

logic [X-1:0][Y-1:0] twoDim;
logic [(X*Y)-1:0]    oneDim;

I want to assign the entirety of twoDim to oneDim i.e. if I wrote something like this:

assign oneDim = twoDim;

And parameter X = 5 then I would expect the behaviour to be the same as the following:

assign oneDim = { twoDim[4], twoDim[3], twoDim[2], twoDim[1], twoDim[0] };

How would this be accomplished succintly in Synthesizable SystemVerilog for all possible values of X, Y (which are int unsigned) ?

CodePudding user response：

For packed aggregate types, you do not need to go through all this trouble. The following will be sufficient. System verilog allows assigning arrays of compatible types (7.6).

   assign oneDim = twoDim;

CodePudding user response：

If you try such assignment you will get an error because the synthetizer does not know about the structure of your 2D array and how it can flatten it. In your case you want to store the rows one after the other, which is called row-major arrangement.

You can produce synthetizable code with a generate for loop:

  localparam X = 10; // N rows
  localparam Y = 20; // N cols
  
  // Note I swapped X and Y dimensions 
  logic [Y-1:0][X-1:0] twoDim;
  logic [(X*Y)-1:0]    oneDim;
  
  genvar i;
  generate 
    for (i = 0; i < X; i = i   1) begin
      assign oneDim[i*Y  : Y] = twoDim[i];
    end
  endgenerate;