How do I enable an arm64 extensions such as FEAT_XNX ?

I'm working on stage 2 page table execution permission on arm64, currently looking into D5.4.6 section of the manual.

It mentions that the XN pair only describe stage 2 controle only when FEAT_XNX is implemented. In my systems it seems that FEAT_XNX is not implemented.

I looked in to MMFR4 and other register to perform the check as mentionned in the manual.

My question would be, how do I "implement" it ? Is it even up to me or it's a feature only available on certain HW ? Can I add this to Qemu ? Could someone explain to me those FEAT_****** things, what is that exactly ? I can't find ressources that talks about it online.

Thanks all

CodePudding user response：

The Arm architecture defines both the base architecture and also extension features. The extension features have names like FEAT_XNX; the exact meaning of each extension is defined in the Arm Architecture Reference Manual for A-profile Architecture.

When QEMU implements an architecture extension, whether you see it in the guest will depend on the guest CPU model you select. For specific CPU types, such as "cortex-a57", QEMU's model implements those architecture features that the real hardware CPU implements. QEMU also has a CPU type "max" -- this is an emulation-only CPU type which has every feature QEMU supports enabled.

As a general rule it is not possible to enable or disable specific architecture extensions on the command line: it can only be done for a few very large features like SVE or SME. (The documentation for these command-line-selectable properties is here: https://www.qemu.org/docs/master/system/arm/cpu-features.html )

At the time of writing, FEAT_XNX is implemented in the QEMU CPU types cortex-a76, neoverse-n1, a64fx, and max.

In guest code, whether you need to specifically "enable" an extension depends on the extension, so you need to check the Architecture Reference Manual for the details. In the case of FEAT_XNX, for instance, there is no system register enable bit. The presence of the feature just means "the CPU will interpret bit 53 of a stage 2 page table descriptor in the way specified by the manual for when FEAT_XNX is present". If the ID registers say that FEAT_XNX is not present, then bit 53 is RES0, and guest software must not create stage 2 page table descriptors where that bit is 1.

CodePudding user response：

The FEAT_XXX Architectural Features documented in Section A of the Architecture Reference Manual (I'm reading version DDI 0487I.a) are hardware features. So if your machine indicates that FEAT_XNX is not implemented, then you can't use it on this hardware.

In the manual's terminology, an "implementation" means, effectively, a hardware chip (or a software emulator).