Verilog "if(test_conditional)" behavior at 'test_conditional' signal transition-CodePudding

Say I have the following:

always @ (posedge clk) beign
...
if (~x) begin
 y<=1'b0
end
...
end

And x, driven in another block, happens to be transitioning from 0 to 1 at the moment I'm checking it. How does if() evaluate in this case? Does it take the starting value of x (0) or the final value of x (1)?

I have looked over other answers to similar questions, but none discuss the particular case when the signal is transitioning. Looking at the waves, the time precision does not allow me to discern if the signal x has settled to 0 or 1.

CodePudding user response：

It depends on how x is driven.

If it is synchronous to the clock signal clk, then the value of x just before the clock edge (0) will be used. In a Verilog simulation, this means that x must be driven off the posedge clk and using a nonblocking assignment:

always @(posedge clk)
    x <= some_expression;

Otherwise, you will have a race condition, and the value of x that is used will be indeterminate: it may be 0 or 1.