1. There are a whole FPGA project, containing pcie module and the rest of the function modules, how on the basis of complete pcie module does not change, the partial loading the rest of the function module


2. PC software currently used are not including bin file (is the way through the JTAG burning FLASH is loaded into a new FPGA program), how to generate bin file, PC software by identifying bin file to properly load the FPGA program