As shown in figure, USES FPGA a CLK signal output, low electricity at ordinary times normal signal to 0 v, now appeared as shown in figure 2, the output signal of the low level is very high, is this why?

CodePudding user response:

Where reference to check the oscilloscope, the oscilloscope level Settings,

CodePudding user response:

The waveform, should be able to see with the superposition of high-frequency ringing on the waveform, the high level raising, low electricity between the negative level, this is typically PCB impedance mismatch, clock source impedance mismatch, general clock source, including active crystals, the clock chip output, buffer the output of the output impedance is very small, such as nearly zero ohm, on the pin of the clock source through a few ohm resistance, can effectively improve the clock waveforms, (impedance mismatch, the clock signal in PCB copper wire at both ends of the reflection and with the original waveform, serious when produce close to 100% of the superposition of reflection)

CodePudding user response:

reference 1st floor xuyaqi029 response:

where reference to check the oscilloscope, oscilloscope level Settings,

Have two AD needed a clock signal from FPGA chip pins, the two pictures are respectively measured the FPGA chip for AD chip CLK waveform, normal produce CLK pins as shown in figure a, abnormal as shown in figure 2

CodePudding user response:

refer to the second floor qq_708907433 response:

the waveform, should be able to see with the superposition of high-frequency ringing on the waveform, the high level raising, low electricity between the negative level, this is typically PCB impedance mismatch, clock source impedance mismatch, general clock source, including active crystals, the clock chip output, buffer the output of the output impedance is very small, such as nearly zero ohm, on the pin of the clock source through a few ohm resistance, can effectively improve the clock waveforms, (impedance mismatch, the clock signal in PCB copper wire at both ends of the reflection and with the original waveform, serious when produce close to 100% of the superposition of reflection)

This problem seems not contact with me?

CodePudding user response:

If the oscilloscope that's right, the second picture clock low level is up to 1.8 v, look from the waveform such as clamping voltage 1.8 v, 2.5 v diode cathode, anode on the clock signal,
If line no wrong, design right, should be the FPGA or AD chip damage breakdown, can have such waveform,

CodePudding user response:

reference 5 floor qq_708907433 reply:

if the oscilloscope and yes, the clock low level was higher in the second picture of 1.8 v, look from the waveform such as clamping voltage 1.8 v, 2.5 v diode anode, cathode on the clock signal,
If line no wrong, design right, should be the FPGA or AD chip damage breakdown, can have such waveform,

ok, thank you