When do the FPGA control AD7768 acquisition DCLK output signal and the drdy signal correctly, but there is no correct dout0-7, dout0-3 low level all the time, dout6-7 high level, dout4 is a cycle of high and low level change, anyway is not correct, did the AD7768?

CodePudding user response:

Using the same AD7768, still see the driver code

CodePudding user response:

Data output, generally does not directly have what problem, only need to pay attention to FORMAT0, FORMAT1 and input formats you need match it,
Key or the control of the chip, what is the pin control (hardware) control or SPI control, inside this if correct, DOUT0 - DOUT7 properly,

CodePudding user response:

The building Lord have a reference code? My DCLK, drdy is correct, the data is out

CodePudding user response:

Stm32 can use AD7768