Procedure is as follows, pin how to allocate


The module responder1323 (RST, CLK, ina, inb, inc, ind, judge, clk_1hz, wei, duan, beep, wei1, duan1, SEC, NRST);
The input CLK, clk_1hz NRST;
Input ina, inb, inc, ind, judge;
Input RST.
The output of the SEC;
The output [3-0] wei;
The output [away] duan;
The output [3-0] wei1;
The output [away] duan1;
The output beep;
Wire [3-0] wei;
Wire [away] duan;
Reg flag, beep, yu;
Reg [beat] shi, ge, data;
Reg [4-0] count;
Wire [3-0] wei1;
Wire [away] duan1;
Reg [1:0] count3;
Fp1323 (NRST, CLK, SEC);
Qd1323 (CLK, RST, judge, wei, duan, ina, inb, inc, ind, clk_1hz);
Fmq1323 (clk_1hz);
Ym1323 (CLK, RST, wei1);
Endmodule

The module fp1323 (NRST, CLK, SEC);
The input CLK, the NRST;
The output of the SEC;
Reg the SEC;
Reg [25:0] CNT;
Always @ (posedge CLK or negedge NRST)
The begin
if(! NRST)/master switch/circuit
The begin
Cnt<=0;
Sec<=0;
End
Else if (CNT==26 'd24999999)//open the master switch
The begin
Cnt<=0;
Sec<=~ the SEC;
End
The else
CntEnd
Endmodule

The module qd1323 (CLK, RST, judge, wei, duan, ina, inb, inc, ind, clk_1hz);
The input CLK, clk_1hz, RST;
Input ina, inb, inc, ind, judge;
The output [3-0] wei;
The output [away] duan;
Reg [3-0] wei;
Reg [away] duan;
Reg flag;
Reg [beat] shi ge;
Reg [4-0] count;
Reg yu;
Always @ (posedge CLK)
The begin
if(! RST)//system reset
The begin
Yu=0;
End
if(! Judge)//host control keys
The begin
Flag=0;//allow vies to answer first
Wei=4 'b1111;//digital tube all not bright
Duan=8 'HFF;
Yu=1;//start the countdown
End
The else
The begin
If (ge==6 'b000000 & amp; & Shi==6 'b000000)//in a waiting state
;
The else
The begin
if(! Ina)//if a vies to answer first
The begin
if(! If flag)//no contest success
The begin
Wei=4 'b1101;
Duan=8 'hf9;//digital tube display 1, representing a vies to answer first success
Flag=1;//vies to answer first sign an effective
End
End
Else if (! Inb)//b vies to answer first circuit
The begin
if(! Flag)
The begin
Wei=4 'b1101;
Duan=8 'ha4;//digital tube display, 2 representative b vies to answer first success
Flag=1;
End
End
Else if (! Inc)
The begin
if(! Flag)
The begin
Wei=4 'b1101;
Duan=8 'hb0;//digital tube display 3
Flag=1;
End
End
Else if (! Ind)
The begin
if(! Flag)
The begin
Wei=4 'b1101;
Duan=8 'h99;//digital tube display 4
Flag=1;
End
End
End
End
End
Always @ (posedge clk_1hz or negedge RST)
The begin
if(! RST)
The begin
count=0;
End
Else if (count & gt; D30=5 ')//timing up to 30 seconds, to stop timing
The count=count;
Else if (yu==1)//trigger condition when yu=1
Count=count + 5 'b1;
End//the following always process for shi and ge decoding circuit, complete the countdown function
Always @ (count)
The begin
If (count>=5 'b10101)//count> 20 when
The begin
Shi=5 'b00000;//shi=0
Ge=5 'b11110 - count;//ge=30 - count
End
Else if (count>=5 'b01011)//10 & lt; Count<=20
The begin
Shi=5 'b00001;//shi=1
Ge=5 'b10100 - count;//ge=20 - count
End
Else if (count>=5 'b00001)//0 & lt; Count<=10
The begin
Shi=5 'b00010;//shi=2
Ge=5 'b01010 - count;//ge=10 - count
End
The else//other situation, i.e. for the count=0
The begin
Shi=5 'b00011;//shi=3
Ge=5 'b0;//ge=0
End
End
Endmodule

The module fmq1323 (clk_1hz);
Input clk_1hz;
Reg flag, beep;
Reg [beat] shi ge;
Reg [1:0] count3;
Always @ (posedge clk_1hz)
If (flag | (shi==0 & amp; & Ge==0))//flag==1, someone vies to answer first success, shi==0 & amp; & Ge==0,
the end of the countdownThe begin//the above two cases buzzer rang a second
If (count3==2 'b1)
The begin
Beep<=0;
Count3 & lt;=count3;
End
The else
The begin
Beep<=1;
Count3 & lt;=count3 + 2 'b1;
End
End
The else
The begin
Beep<=0;
Count3 & lt;=0;
End
Endmodule





The module ym1323 (CLK, RST, wei1);
The input CLK, RST;
The output [3-0] wei1;
Reg [3-0] wei1;
Reg [beat] shi, ge, data;
Reg [away] duan1;
Always @ (CLK)
The begin
if(! RST)
Wei1=4 'b0000;
Else if (CLK)
The begin
Wei1=4 'b0111;
data=https://bbs.csdn.net/topics/ge;
End
The else
The begin
Wei1=4 'b1011;
data=https://bbs.csdn.net/topics/shi;
End
End
Always @ (data)//decoded digital display, digital tube, a total of anode (duan1)
The begin
Case (data)
6 'b000000: duan1=8' b1100_0000;
6 'b000001: duan1=8' b1111_1001;
6 'b000010: duan1=8' b1010_0100;
6 'b000011: duan1=8' b1011_0000;
6 'b000100: duan1=8' b1001_1001;
6 'b000101: duan1=8' b1001_0010;
6 'b000110: duan1=8' b1000_0010;
6 'b000111: duan1=8' b1111_1000;
6 'b001000: duan1=8' b1000_0000;
6 'b001001: duan1=8' b1001_0000;
Default: duan1=8 'b1111_1111;
Endcase
End
endmodule

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CodePudding user response:

The clock and reset with special pin will be saved, other pin press convenient wiring can,