A stopwatch shows time for four decimal number, from 0.00.0 ~ 9.59.9 (points. Seconds. 100 milliseconds) cycle count; The CLR, contains a reset signal is a stopwatch to return 00.0; Contains a start the go signal, control start or stop counting; Up to add an additional signal, is used to control direction of counting counting (addition or subtraction count) code written in vivado,
Completed
Modulestop_watch (inputclk inputgo, CLR, output [3-0] d2 and d1, do; ); localparamCOUNT_VALUE=https://bbs.csdn.net/topics/5000000; Reg [22:0] ms_reg; Reg [3-0] d2_reg, d1_reg d0_reg; Regdp; Wirems_tick; Reg [3-0] d2_next, d1_next d0_next; Always @ (posedgeclk) begin the if (CLR==0) begin ms_reg <=23 'b0; D2_reg <=4 'b0; D1_reg <=4 'b0; D0_reg <=4 'b0; End elseif (go==1) begin d2_reg <=d2_next; D1_reg <=d1_next; D0_reg <=d0_next; If (ms_reg CodePudding user response:

Verilog? You paste the code difficult to read,,,,