To do LDPC coding is a small place, just learn verilog is not very clear what to do, did Daniel taught the
1. The system clock 50 MHZ,
2. According to the number of input 7, according to the specified algorithm have 6 * number 26,
3. Input the number 7 parallel input and output of the serial number 156 output,
4. Design module have the ability to work in a row, performs a single operation time not more than 200 clock, namely every 200 clock cycles, the user can enter the new number 7,
The concrete implementation of the module of signal as follows
The Module matrix_gen (
CLK,
RSTN,//reset signal, low effective

Param_ena,//input parameters can make the signal, when effective, the parameters of the port will be read
Pa, pb, PC, pd, PE, pf, pmod,//set the seven parameters of the signal

Data generated dataout,//
Datacnt,//the data count
Dataena//data valid instructions
);
The input CLK.
Input RSTN;
Input ena.

Input [away] pa, pb, PC, pd, PE, pf;
Input [Wednesday] pmod;
Input param_ena;

The output [away] dataout;
The output dataena;
The output [away] datacnt;

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I am also doing LDPC codes based on FPGA, and asked