The module LOOP_lpf (CLK, rst_n x_in, y_out, temp);
The input CLK, rst_n;//the clock and reset signal
Input [26:0] x_in;//input: phase output module
The output/26:0 y_out;//the loop filter output
The output/26:0 temp;
Reg [26:0] temp;
Reg [26:0] y_out;

Always @ (posedge CLK or negedge rst_n)
if(! Rst_n)
The begin
Y_out & lt;=0;
Temp & lt;=0;
End
The else
The begin//for loop filter operation
Y_out & lt; 4={{{x_in [26]}}, x_in [David]} - {{7 {x_in [26]}}, x_in [then]}.//
Temp & lt;=temp + {{{10 x_in [26]}}, x_in [though]}.//
End

endmodule

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