Always @ (posedge sys_clk or negedge sys_rst_n) begin
if(! The begin sys_rst_n)
Clk_cnt & lt; D0=4 ';
Dri_clk & lt;=1 'b1;
End
Else if (clk_cnt==CLK_DIVIDE/2-1 'd1) begin
Clk_cnt & lt; D0=4 ';
Dri_clk & lt;=~ dri_clk;
End
The else begin
Clk_cnt & lt;=clk_cnt + 1 'b1;
Dri_clk & lt;=dri_clk;
End
End
Some beginners don't understand the code above can help explain

CodePudding user response:

The simulation control waveform is well understood, and the FPGA title wrong number is