FIFO RAM, is the nature of first in first out
Important parameters: the fifo depth (it's need to how much a simple data)
Fifo bits wide (each data bits wide)
FIFO has two kinds of synchronous and asynchronous, synchronous clock is the same, namely, speaking, reading and writing asynchronous read and write the clock is not the same
Synchronous FIFO with less, can be used as a data cache
Asynchronous FIFO can solve the problem of the clock domain, the application should be according to the actual situation for the FIFO depth can
This to design an asynchronous FIFO, depth of 8, bit width is 8.
Code is Simulation study and short Techniques for Asynchronous FIFO Design Clifford e. Cummings, Sunburst Design, Inc., this article,
Baidu search is easy to find, although is written in English but really worth studying,
Below I will analyze the main points of the design, as well as a summary of his own learning process, to communicate, make progress together with you,
Two, design points,
1, read how empty signal? Write full signal how?
Read: empty signal reset, read pointer and the write pointer is equal, read empty signal effectively (address this pointer is read, write address) when the read pointer to catch up with the write pointer, the write pointer is equal to the read pointer means the final data is read, read the empty signal effective
Write full signal: when the write pointer is more than the read pointer to a circle, the write pointer is equal to the read pointer means write full, now write full signal effective
We will find to read write pointer is equal to the read pointer is the empty condition, write full condition is also write pointer is equal to the read pointer, how to distinguish?
Solution: defines of the pointer many a
For example: suppose you want to design a depth of 8 asynchronous FIFO, then define the read/write pointer only need three (2 ^ 3=8) will do the trick,
But we will be in the design of pointer design into four bits wide, the role of the highest level is to distinguish is empty or full, read specific theory 1 below
The same as the highest, the rest a considered read empty
When the highest level is different, the rest is a same think with
Note: theory 1 trial is empty with comparative judgment between binary number,
But this article is not such a comparison, but with the theory of 2, here I explain
Because the articles in the design of judgment is whether the read pointer is equal to the write pointer, use the read/write pointer gray code form (why?/why not explain later with gray code), then if problems with the theory of the above 1,
If it is only because the gray code is mirror symmetrical, according to the highest level is to differentiate between the same read or write full empty is problematic, I said slowly, see figure 1
Green frames is 0-15 gray code, gray code with red lines divided into fluctuation two parts
Neighbouring bits by observing the gray code change only one bit at a time, and the fluctuation two parts, in addition to the highest level, on the other hand, the rest are all about the red mirror symmetry,
7 - & gt; 8, gray code from 0100 - & gt; 1100, only the highest change the rest of the a same
6 - & gt; From 0101-9, gray code & gt; 1101, only the highest change the rest of the a same
By analogy, why want to say that mirror?
Imagine if the read pointer to eight, write pointer to 7, we can know empty status at the moment is not read nor write full state
But if at the moment to judging theory 1, look to see what would happen, let us have a set of
Gray code of 7 and 8 of the highest level of gray code is different, the rest is the same, so determine to write full, this is wrong, also apply in 6 and 9, 5 and 10 also can appear misjudgment,
Gray code so use to judge whether to read or write full theory should be used when the 2 empty, the highest level and high times are equal, specific as follows:
When the highest and the same time high, the rest of the same thought to be reading an empty
When the highest level and different time high, the rest is the same as write full
Repair: theory 2 gray code this judgment method is suitable for use to judge is empty with
If you don't want to use gray code is in the actual design, can use gray code to read and write address to a clock domain then gray code into a binary number again after 1 compared with theory,,
2, because it is the design of asynchronous FIFO, read and write the clock is not the same, and fill in the read empty signal, will involve the issue of the clock domain, how to solve?
The clock domain problem: we have already mentioned above through empty compared to read and write Pointers to judge the read and write full signal
But read pointer belongs to the clock domain, the write pointer is belong to write clock domain, and the clock domains, asynchronous FIFO, speaking, reading and writing is asynchronous,
If you will read clock domain pointer and write clock domain do anything with the write pointer is not a direct comparison is definitely wrong, so we need to synchronize after processing seed compare
Solution: two-stage synchronization + gray code register
The synchronization process has two:
(1) will be written to the write pointer synchronous clock domain to read clock domain, will write pointer and read after the synchronous clock domain read pointer comparison have read empty signal
(2) to read clock domain pointer to write clock domain, will synchronize the read pointer after comparing with write clock domain pointer to produce full signal
Thought is to use two level register synchronization, simply is to make two beats, believe that a little early to know all by heart, no longer to do more to explain, don't understand can look at the code combination of understanding,
Just so simple synchronization can? No no no, terrible metastable still waiting for you,
If we just use binary encoding of read/write pointer to complete the above two kinds of synchronization is not enough, use the gray code is more appropriate, why?
Because binary coded pointer when jump to change together may be a number of data, such as binary 7 - & gt; 8-0111 - & gt; 1000, in the process of jump four all changed, so it is easy to produce burr, such as
Write pointer and read pointer of asynchronous FIFO belong to different clock domains, this pointer in the synchronization process is very easy to get wrong, such as writing pointer when jumping from 0111 to 1000 four change at the same time, read the clock like this in the write pointer after the write pointer synchronization can be a value of 0000-1111, a total of 2 ^ 4 possible, all of which are uncontrollable, you are not sure which values will appear, and the error probability is very big, how to do? When the gray code function and the coding feature of gray code is adjacent to a change in only one bit at a time, so that at the time of pointer synchronization, there are only two possible situations: 1. The pointer synchronization is correct, just what we want to; 2. The pointer synchronization errors, for example assumes that the gray code to write pointer from 000 - & gt; 001, will write pointer to read clock domain synchronization error, error of the result can only be 000 - & gt; 000, because the adjacent bits of gray code every time there is only one change, the error result is actually write pointer not jump remains the same, what we care about is the error judgment error will not lead to read is empty? The answer is no, is to make the most empty sign at the time of FIFO is not really empty, without the possibility of empty reading, so after gray code to ensure the synchronization of read/write pointer even in the case of the error is still able to guarantee the correctness of the FIFO function, in the process of synchronization metastable impossible to eliminate, but we just make sure it won't affect our normal work,
3, due to the design of read/write pointer register with at least two levels of synchronization, synchronization will consume at least two clock cycles, is bound to make judgment, empty or full a delay, it will not lead to a design error?
Asynchronous FIFO through comparing the read/write pointer to fill empty, but the read/write pointer belong to different clock domains, so need to compare before a read/write pointer to synchronous processing,
Will write pointer to read clock domain and the read pointer comparison FIFO empty state judgment, because in the synchronous write pointer takes time, and in the synchronization of time may also be written to the new data, so the synchronization of the write pointer must be less than or equal to the current actual write pointer, so judge FIFO is empty at this time is not necessarily a vacuum, so that more conservative, a total of empty read will not happen, although will affect the performance of the FIFO, but will not go wrong, the same will read pointer to write clock domain and the write pointer is the FIFO full state judgment, synchronous after the read pointer must be less than or equal to the current pointer, so judge FIFO for full is not necessarily true full right now, it is more conservative, so we can ensure FIFO feature: FIFO empty after can not continue to read, FIFO can't continue to write, after full summary for asynchronous logic to the synchronization logic inevitably require additional clock overhead, which can lead to fill empty conservative, but conservative does not mean error, so write performance will be slightly, but will not make a mistake,
For example: in most cases, the clock is not of the same frequency at the ends of the asynchronous FIFO, write or read fast slow, slow or read write fast, slow synchronization clock domain to miss pointer clock domain will not happen quickly, but the pointer from the clock synchronization to slow clock domains when there may be a pointer omission, for example in read write slow fast, for example, the full mark judgment when you need to read pointer to write clock domain, because reading slow write faster, so there won't be read pointer omission, synchronous clock cycle, so the read pointer after synchronization delay (less than or equal to) the current address, so may be produced in advance full marks, is not really full, full of empty sign judgment when need to write pointer to read pointer, because reading slow write faster, so when the read clock synchronization write pointer is bound to be part of the write pointer is missing, we don't have to care about that what they missed the write pointer, we care about is to miss the pointer affect FIFO empty logo? Write pointer from 0 to 10, for example, read clock domain synchronization capture only 3,5,8 during this three write pointer and missed other pointer, when synchronous to the write pointer, real write pointer might have wrote 10, the equivalent of reading before the clock domain could perceive the cases, the write clock domain may be secretly wrote data to the FIFO, whether it is empty is not really empty would happen, when miss pointer also have no influence on the logical operation of FIFO,
4, how many binary code into a gray code
Binary code into binary gray code, and its law is retains the highest level of the binary code as gray code of the highest, and The Times of high level in gray code to binary code and time in exclusive or high, and the rest you gray code and method for the similar time high,
I'll rephrase the simpler description
Binary number 1 1 1 0 0
Binary number moves to the right one, vacancy to fill 0 0 0 1 1
Exclusive or operation 1 1 1 0 1
So that you can achieve binary to the transformation of gray code, summary is shifting and xor, verilog code implementation is 1: assign wgraynext=(wbinnext> 1) ^ wbinnext;
Is very simple,
5. Different in-depth thinking of clock rate synchronization
When an asynchronous FIFO to synchronize two different clock domains, apparently two clock speed is different, consider when a fast clock domain signal synchronization to slow clock domain may exist when count jump, because in a cycle of clock domain slow fast clock domain may count has increased many times, thus leads to the following two questions:
When synchronous gray code if gray code value added two however was just the one sample will appear more bits of data changes, this situation will lead to more bit data synchronization problem?
The answer is no, at the time of synchronization bit more data when multiple data bits along the change in rise will appear problem, but for fast clock domain pointer of gray code written in one clock cycle only change one, at most, so around slow clock domain can have a bit change,
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