In the test signal integrity between FPGA and phy, found the eye diagram quality has a problem, the graphics below
Test method, the diagram below, already very close to the receiver, and the fpga internal to the euro 100 matches
Really don't know the problem is how to produce, please great god guidance!
CodePudding user response:
Regulation under the FPGA driver ability, the current is how many?
CodePudding user response:
Hello, have tried to add the internal pull-up, but no effect