The module alu (a, b, aluctrl, zero, signs and result, CLK, SSL, SRL, sra, SLLV, SRLV, srav, s);
Input [31:0] a, b;
Input [Wednesday] s;
Input [2-0] aluctrl;
The input CLK, SSL, SRL, sra, SLLV, SRLV, srav;
The output 31:0 result, sign;
The output zero;

Wire [31:0] wire_alu;
Reg [31:0] resultreg;
Reg [31:0] c;
Reg d;
Integer (I);

Always @ (*)
The begin
If (sra)
The begin
D=b [31];
C=b;
for(i=0; iC={d, c [2]}.
End
Else if (srav)
The begin
D=b [31];
C=b;
for(i=0; iC={d, c [2]}.
End
End

The assign wire_alu=
(aluctrl==3 'b000)? A + b:
(aluctrl==3 'b001)? A - b:
(aluctrl==3 'b010)? A | b:
(aluctrl==3 'b011)? {b [15:0], 16 'b0} :
B100 (aluctrl==3)? A& B:
(aluctrl==3 'b101)? A& | ~ ~ b a& B:
(aluctrl==3 'b110)? ~ (a | b) :
(aluctrl==3 'b111 & amp; & SSL)? B(aluctrl==3 'b111 & amp; & SRL)? b> S:
(aluctrl==3 'b111 & amp; & Sra)? C:
(aluctrl==3 'b111 & amp; & SLLV)? B(aluctrl==3 'b111 & amp; & SRLV)? b> A:
(aluctrl==3 'b111 & amp; & Srav)? C:
32 'b0;

Always @ (posedge CLK)
Resultreg<=wire_alu;

The assign zero=(wire_alu==0);
The assign sign={31 'b0, wire_alu [31]};
Assign the result=resultreg;

endmodule

CodePudding user response:

Error (10119) : Verilog HDL Loop Statement Error at alu. V (28) : Loop with non - constant terminating condition exceeds 5000 iterations, the built - in limit

CodePudding user response:

for(i=0; i

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