Home > other >  The FPGA timing optimization problem
The FPGA timing optimization problem

Time:09-16

Excuse me if there is excessive program logic series set up time is not met, in the static timing report processing program with the method of assembly line processing, is there any other way to deal with the logical progression of too much question

CodePudding user response:

Information about timing problems online a lot, too many classes, you can look at first, what's the problem, determine your design and then suit the remedy to the case, the general questions, is, no one can give you the actual solution to recommend you see,
https://blog.csdn.net/kaopuguyue110/article/details/71079248

CodePudding user response:

The assignment under the process of
Using synchronization logic, improve master clock
Optimization of logic circuit

CodePudding user response:

Split into multiple modules, multi-purpose in parallel

CodePudding user response:

retming
  • Related