Open source code, reference net, debugging for two days, in written to address and pointer register and configure config registers, always returns nack, don't know if it's the wrong part,

Ads1115 header file

 
# # ifndef _ADS1115_H 
# define _ADS1115_H 

# include "stm32f10x. H" 
# include "sys. H" 


# define SCL PBout (6) 
# define SDA_OUT PBout (7) 
# define SDA_IN PBin (7) 

# define TRUE 1 
# define FALSE 0 

//* * * * * * * * * * * * * ADDR Initial * * * * * * * * * * * * * * * * * * * */
# define ADDRESS ADDRESS_0//ADDR PIN - & gt; GND 
# define ADDRESS_W ADDRESS | 0 x00//write ADDRESS 
# define ADDRESS_R ADDRESS | 0 x01//read ADDRESS 

/* * * * * * * * * * * * * Config Initial * * * * * * * * * * * * * * * * * * * * */
# define OS OS_1 
# define MUX_A0 MUX_4//AINp=AIN0, AINn=GND 
# define MUX_A1 MUX_5//AINp=AIN1 and AINn=GND 
# define MUX_A2 MUX_6//AINp=AIN2, AINn=GND 
# define MUX_A3 MUX_7//AINp=AIN3, AINn=GND 
# define PGA PGA_0//FS=6.144 V 
# define MODE MODE_0//Continuous conversion MODE 
# define DR DR_7//Data Rate=860 
# define COMP_QUE COMP_QUE_3 


/* * * * * * * * * * ADDR macro definition * * * * * * * * * * * * * * */
# define ADDRESS_0 0 x90//ADDR PIN - & gt; GND 
# define ADDRESS_1 0 x92//ADDR PIN - & gt; VDD 
# define ADDRESS_2 0 x94//ADDR PIN - & gt; SDA 
# define ADDRESS_3 0 x96//ADDR PIN - & gt; SCL 


/* * * * * * * * * * * * POINTER REGISTER * * * * * * * * * * * * * * * * */
# define Pointer_0 0 x00//Convertion register 
# define Pointer_1 0 x01//Config register 
# define Pointer_2 0 x02//Lo_thresh register 
# define Pointer_3 0 x03//Hi_thresh register 

/* * * * * * * * * * * * CONFIG REGISTER * * * * * * * * * * * * * * * * */
# define OS_0 0 x0000 
# define OS_1 0 x8000 

# define MUX_0 0 x0000//AINp=AIN0, AINn=AIN1 
# define MUX_1 0 x1000//AINp=AIN0, AINn=AIN3 
# define MUX_2 0 x2000//AINp=AIN1 and AINn=AIN3 
# define MUX_3 0 x3000//AINp=AIN2, AINn=AIN3 
# define MUX_4 0 x4000//AINp=AIN0, AINn=GND 
# define MUX_5 0 x5000//AINp=AIN1 and AINn=GND 
# define MUX_6 0 x6000//AINp=AIN2, AINn=GND 
# define MUX_7 0 x7000//AINp=AIN3, AINn=GND 

# define PGA_0 0 x0000//FS=6.144 V 
# define PGA_1 0 x0200//FS=4.096 V 
# define PGA_2 0 x0400//FS=2.048 V 
# define PGA_3 0 x0600//FS=1.024 V 
# define PGA_4 0 x0800//FS=0.512 V 
# define PGA_5 0 x0a00//FS=0.256 V 
# define PGA_6 0 x0c00//FS=0.256 V 
# define PGA_7 0 x0e00//FS=0.256 V 

# define MODE_0 0 x0000 
# define MODE_1 0 x0100 

# define DR_0 0 x0000//Data Rate=8 
# define DR_1 0 x0020//Data Rate=16 
# define DR_2 0 x0040//Data Rate=32 
# define DR_3 0 x0060//Data Rate=64 
# define DR_4 0 x0080//Data Rate=128 
# define DR_5 0 x00a0//Data Rate=250 
# define DR_6 0 x00c0//Data Rate=475 
# define DR_7 0 x00e0//Data Rate=860 

# define COMP_MODE_0 0 x0000 
# define COMP_MODE_1 0 x0010 

# define COMP_POL_0 0 x0000 
# define COMP_POL_1 0 x0008 

# define COMP_LAT_0 0 x0000 
# define COMP_LAT_1 0 x0040 

# define COMP_QUE_0 0 x0000 
# define COMP_QUE_1 0 x0001 
# define COMP_QUE_2 0 x0002 
# define COMP_QUE_3 0 x0003 



Void Write_1_Byte (char DataByte); 
Char Write_N_Byte (char * writebuffer, u8 n); 
Char Read_1_Byte (void); 
Void Read_N_Byte (int * readbuff, u8 n); 
Void InitADS1115 (u8 S_MUX_0, u8 S_MUX_1); 
U8 WriteWord (void); 
U8 ReadWord (void); 
Float ADS1115 (u8 S_MUX_0, u8 S_MUX_1); 


# endif 

Iic part function

 
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
* can work: iic1 start signal 
No 
 * and number:* the return value: no 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Void Iic1_Start (void) 
{
//mode output 
Iic1_Mode (GPIO_Mode_Out_PP); 

SCL_PB6=1; 
SDA_OUT_PB7=1; 
Delay_us (5); 

SDA_OUT_PB7=0; 
Delay_us (5); 

//SDA and SCL for low clamped bus 
SCL_PB6=0; 

} 
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
* can work: iic1 stop signal 
No 
 * and number:* the return value: no 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
Void Iic1_Stop (void) 
{
//mode output 
Iic1_Mode (GPIO_Mode_Out_PP); 

SCL_PB6=0; 
SDA_OUT_PB7=0; 
Delay_us (5); 

SCL_PB6=1; 
Delay_us (5); 

//SDA and SCL is high level, bus free 
SDA_OUT_PB7=1; 

} 
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
* can work: iic2 receive a data 
No 
 * and number:* the return value: ack 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
U8 Iic2_Recv_Ack (void) 
{
U8 ack. 

//mode input 
Iic2_Mode (GPIO_Mode_IN_FLOATING); 

SCL=0; 
Delay_us (5); 
SCL=1; 

If (SDA_IN==1) 
{
Ack=1; 
} 
The else 
{
Ack=0; 
} 
Delay_us (5); 
SCL=0; 

Return the ack; 
} 

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