Xilinx_linux driver support PHY models is DP83822, recognizes the PHY models but is unable to ping,

Don't know how to write device tree configuration, connection mode and zedboard use marallmavell, 88 e1510 completely consistent, DP83822 phy address is 3 start printing as shown in the following attachments, corresponding DTB files is to use the zynq - zed. DTB

Start to print information such as the attachment, and the corresponding DTS file, please everyone a great god help thank you!

Macb e000b000. Ethernet eth0: Cadence GEM rev 0 x00020118 at 0 xe000b000 irq 27 (00:0 a: 35:00:01:22)
TI DP83822 10/100 Mbps PHY e000b000. Ethernet - FFFFFFFF: 1 f: attached PHY driver/TI DP83822 10/100 Mbps PHY (mii_bus: phy_addr=e000b000. Ethernet - FFFFFFFF: 1 f, irq=POLL)

IPv6: ADDRCONF (NETDEV_UP) : eth0: the link is not ready

Xilinx First Stage Boot Loader
Release 2017.4 Oct 2019-28 16:56:08
Devcfg driver the initialized
Silicon Version 3.1
The Boot mode is SD
SD: rc=0
SD Init Done
Flash Base Address: 0 xe0100000
Reboot the status register: 0 x60400000
Multiboot Register: 0 x0000c000
Image Start Address: 0 x00000000
Partition Header Offset: 0 x00000c80
Partition the Count: 3
Partition Number: 1
The Header Dump
Image Word Len: 0 x000f6ec0
Data Word Len: 0 x000f6ec0
Partition Word Len: 0 x000f6ec0
The Load Addr: 0 x00000000
The Exec Addr: 0 x00000000
Partition Start: 0 x000065d0
Partition Attr: 0 x00000020
Partition Checksum Offset: 0 x00000000
Section Count: 0 x00000001
Checksum: 0 xffd14b7e
Bitstream
In FsblHookBeforeBitstreamDload function
PCAP: StatusReg=0 x40000a30
PCAP: device ready
PCAP: Clear the done
The Level Shifter Value=https://bbs.csdn.net/topics/0xA
Devcfg Status register=0 x40000a30
PCAP: Fabric is Initialized done
PCAP register dump:
PCAP CTRL xf8007000 0:0 x4c00e07f
PCAP xf8007004 LOCK 0:0 x0000001a
PCAP xf8007008 CONFIG 0:0 x00000508
PCAP xf800700c ISR 0:0 x0802000b
PCAP xf8007010 IMR 0:0 XFFFFFFFF
PCAP xf8007014 STATUS 0:0 x00006a30
PCAP DMA SRC xf8007018 ADDR 0:0 x00100001
PCAP DMA DEST xf800701c ADDR 0:0 XFFFFFFFF
PCAP DMA SRC xf8007020 LEN 0:0 x000f6ec0
PCAP DMA DEST xf8007024 LEN 0:0 x000f6ec0
PCAP ROM SHADOW CTRL xf8007028 0:0 XFFFFFFFF
PCAP xf800702c MBOOT 0:0 x0000c000
PCAP SW xf8007030 ID 0:0 x00000000
PCAP xf8007034 UNLOCK 0:0 x757bdf0d
PCAP xf8007080 MCTRL 0:0 x30800100

The DMA Done!

The FPGA Done!
In FsblHookAfterBitstreamDload function
Partition Number:
2The Header Dump
Image Word Len: 0 x0001fc48
Data Word Len: 0 x0001fc48
Partition Word Len: 0 x0001fc48
The Load Addr: 0 x04000000
The Exec Addr: 0 x04000000
Partition Start: 0 x000fd490
Partition Attr: 0 x00000010
Partition Checksum Offset: 0 x00000000
Section Count: 0 x00000001
Checksum: 0 xf7ea3426
Application
Handoff Address: 0 x04000000
In FsblHookBeforeHandoff function
SUCCESSFUL_HANDOFF
FSBL Status=0 x1


U - the Boot 2018.01 (Nov 2019-04 14:45:31 + 0800)

Model: Zynq Zed Development Board,
Board: Xilinx Zynq
Silicon: v3.1
DRAM, ECC disabled 512 MiB
MMC: sdhci @ e0100000:0 (SD)
SF: Detected n25q128 with page size of 256 Bytes, erase the size 64 KiB, total 16 MiB
* * * Warning - bad CRC, using the default environment

In: serial @ e0001000
Out: serial @ e0001000
Err: serial @ e0001000
Net: ZYNQ GEM: e000b000, phyaddr 0, interface rgmii - id
Eth0: Ethernet @ e000b000
Hit any key to stop autoboot: 0
Zynq>
Zynq>
Zynq>
Zynq> Mdio list
Eth0:
1 f - Generic PHY & lt; - & gt; Ethernet @ e000b000
Zynq> Mii device
MII devices: 'eth0'
The Current device: 'eth0'
Zynq> Mii info
PHY 0 x1f: OUI=0 x80028, Model=0 x24, Rev=0 x00, 10 baset, HDX
Zynq> Mii dump 1 0 f
0. (3100) - PHY control register -
(8000-0000) 0.15=0 reset
(4000-0000) 0.14=0 loopback
(2040:2000) 0. 6, 13=b01 speed selection=100 Mbps
(1000:1000)=0.12 1 A/N enable
(0800:0000) 0.11=0 power - down
(0400-0000) 0.10=0 isolate
(0200:0000) 0. 9=0 restart A/N
(0100:0100) 0. 8=1 duplex=full
(0080:0000) 0. 7=0 collision test enable
(0000) 003 f: 0. 5-0=0 (reserved)


Zynq> Mii dump 1 f 1
1. (7849) - PHY status register -
(8000:0000) 1.15=0 100 base - T4 able
(4000:4000) 1.14=1 100 base - X full duplex able
(2000:2000) 1.13=1 100 base - X half duplex able
(1000:1000) 1.12=1 10 Mbps full duplex able
(0800:0800) 1.11=1 10 Mbps half duplex able
(0400:0000) 1.10=0 100 base - T2 full duplex able
(0200:0000) 1. 9=0 100 base - T2 half duplex able
(0100:0000) 1. 8=0 extended status
(0080:0000) 1. 7=0 (reserved)
(0040:0040) 1. 6=1 MF preamble suppression
(0020:0000) 1. 5=0 A/N complete
(0010:0000) 1. 4=0 remote fault
(0008:0008) 1. 3=1 A/N able
(0004:0000) 1. 2=0 the link status
(0002:0000) 1. 1=0 jabber detect
(0001:0001) 1. 0=1 extended "capabilities


Zynq> Mii dump 1 f 2
nullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnullnull