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Verilog conditional statement

Time:09-22

Why small white, please the following program if statements (conditional statements) else behind the content of the simulation of always can't perform??
Always @ (posedge CLK)
The begin
If (count==1 'b0 | | 1' b1)
x<=a;
The else
The begin
If (x % 2==0)
x<=x/2;
The else
x<=x * 3 + 1;
NumEnd
End
Endmodule


CodePudding user response:

Always @ (posedge CLK)
The begin
if (count==1 'b0 | | 1' b1) //this condition no matter how, you will be set up, so, no matter what happens, are executed x=a, blue instruction execution less than
x<=a;
The else
the begin
If (x % 2==0)
x<=x/2;
The else
x<=x * 3 + 1;
NumEnd
End
endmodule

CodePudding user response:

Solved!!!!! thank you
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