The module led1 (CLK, RST, led);

The input CLK, RST;
The output of led;

The parameter time_1=27 'd5000_0000;

Reg [26:0] CNT;
Reg the led;

Always @ (posedge CLK or negedge RST)
if(! RST)
CNT & lt; D0=27 ';
Else if (CNT==time_1)
CNT & lt; D0=27 ';
The else
CNT & lt; CNT=+ 1 'b1;

Always @ (posedge CLK or negedge RST)
if(! RST)
The led & lt;=1 'b1;
Else if (CNT==time_1)
The led & lt;=~ led;

Endmodule


The simulation

` timescale ns/1 ns
The module led1_vlg_tst ();
Reg eachvec;
Reg the CLK.
Reg RST.
Reg CNT.
Wire led;

Led1 i1 (
CLK (CLK),
Leds (led),
RST (RST)
);
Initial
The begin

CLK=0;
RST=0;
# 100
RST=1;
End
Always # 1 CLK=~ CLK;
Endmodule
Simulation of CNT is x!!!!!

CodePudding user response:

Although the program is very simple, no one wants to see but no comment!

CodePudding user response:

Program there is no problem, now whether you simulation timeline small, CNT can't up to 50000000

CodePudding user response:

CNT is decimal 'd; You add 1 'b1; Certainly an error

CodePudding user response:

Simulation with CNT for x means that you didn't give the CNT an initialization value, in addition, your module led1 (CLK, RST, led); Definition of CNT there is lead, do you see the simulation module of CNT is uninitialized CNT

CodePudding user response:

Initialize the CNT value is wrong, can't get into CNT + 1