Home > other >  VHDL pulse laser ranging
VHDL pulse laser ranging

Time:09-23

@] [VHDL (pulsed laser ranging)
This is a laser rangefinder in the receiving module and display module between the small module

To solve the meanings and roles of the code

The LIBRARY IEEE.
USE the IEEE. STD_LOGIC_1164. ALL;


The ENTITY COUNTER IS
The PORT
(
ST, CLK, TR, REC: IN STD_LOGIC;
COUNT: BUFFER INTEGER RANGE 0 TO 65535
);
END COUNTER;



The ARCHITECTURE OF A COUNTER IS
SIGNAL COUNT_REG: INTEGER RANGE 0 TO 65535; Values of 0 to 65535 - signal COUNT_REG
The BEGIN
The PROCESS (ST, CLK, TR, REC)
The BEGIN
IF (ST='1') THEN
COUNT_REG & lt;=0;
COUNT<=0;
The ELSE
IF (CLK 'EVENT AND CLK=' 1 ') THEN, when the clock signal is rising along the
IF (TR='0') THEN - IF the TR is 0, the
COUNT_REG & lt;=COUNT_REG; - COUNT_REG constant
The ELSE - otherwise
IF ((TR) AND REC='0') THEN - IF the TR AND REC are 0. The
COUNT_REG & lt;=COUNT_REG + 1; 1
- COUNT_REGThe ELSE - otherwise
IF ((TR AND REC)='1') 1, THEN - IF the TR AND REC,
COUNT_REG & lt;=COUNT_REG; - COUNT_REG constant, the output COUNT_REG
COUNT<=COUNT_REG;
END IF;
END IF;
END IF;
END IF;
END IF;
END the PROCESS.
END A;

CodePudding user response:

The timing is not complicated, but depends on the specific meaning, this program also look not to come out,
  • Related