Does the singaltap on FPGA can automatically the AD conversion data stored in RAM?
Or someone can tell me the first the thinking of a figure, see me is a problem with the circuit diagram is drawn

CodePudding user response:

Lz didn't seem to clear up the ADC is what?

CodePudding user response:

This is the conversion rate of different adc and dac series work together, the middle do rate matching with ram