Earlier still can see the normal simulation, is timing, pause and countdown waveform
Now is this bug report

The following is the code:
Function, see the picture

` timescale ns/1 ps
The module stopwatch (CLK, RST, sw, m1, m2, s1, s2);

The input CLK, RST;
The output reg m1, m2, s1, s2;//1 said 10, 2 said bits
Input (2-0) sw.//button press 2: low level said min, 1: the SEC, 0: pause/start
The parameter count_on=3 'd0, settime=3' d1, pause=3 'd2, clear=3' d3, count_down=3 'd4.
The parameter a=3 'b000, b=3' b001, c=3 'b010, d=3' b100, e=3 'b011, f=3' b101, g=3 'b110, h=3' b111;
Reg [2-0] mode;

Always @ (posedge CLK) begin
Case (sw)
A: the begin mode<=the clear; End
B: the begin mode<=the clear; End
E: the begin mode<=settime; End
F: the begin mode<=settime; End
G: the if (mode==count_on) begin mode<=pause; End
Else if (mode==pause) begin mode<=count_on; End
Else if (mode==settime) begin mode<=count_down; End
Else if (mode==count_down) begin mode<=pause; End
Else if (mode==clear) begin mode<=count_on; End
H: begin mode<=pause; End
Default: begin mode<=pause; End
Endcase
End


Always @ (posedge CLK) begin
Case (mode)//
Count_on://timing s
The begin
if (! RST) s2 & lt;=s2;
Else if (s2==9)
S2 & lt;=0;
The else
S2 & lt;=s2 + 1;
if(! RST) s1 & lt;=s1;
Else if (s2==9)
The begin
If (s1==5)
S1 & lt;=0;
The else
S1 & lt;=s1 + 1;
End
//-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- timing part m
if(! RST) m2 & lt;=m2;
Else if (s1==5 & amp; & S2==9)
The begin
If (m2==9)
M2 & lt;=0;
The else
M2 & lt;=m2 + 1;
End
if(! RST) m1 & lt;=m1;
Else if (s1==5 & amp; & S2==9)
The begin
If (m2==9)
The begin
If (m1==9)
M1 & lt;=0;
The else
M1 & lt;=m1 + 1;
End
End
End

//-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --

//-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- the countdown input section
Settime:
The begin
S1 & lt;=0; S2 & lt;=0; M1 & lt;=0; M2 & lt;=0;
If (sw [1]==0) begin
The begin//if3
If (s1!=5) begin//if2
If (s2!=9) begin s2 & lt;=s2 + 1; End//if1
The else begin s2 & lt;=0; S1 & lt;=s1 + 1; End
End//else1
The else begin s1 & lt;=0; End//else2
End


If (sw [2]==0) begin
If (m1!=9) begin//if2
If (m2!=9) begin m2 & lt;=m2 + 1; End//if1
The else begin m2 & lt;=0; M1 & lt;=m1 + 1; End
End//else1
The else begin m1 & lt;=0; End//else2
End
End
End



//-- -- -- -- -- -- -- -- -- -- -- -- the countdown m1, m2: s1 s2 12:30
Count_down:
The begin//0
If (s1==0 & amp; S2==0 & amp; M1==0 & amp; M2==0) begin mode<=the clear; End
Else if (! RST)
The begin//1
If (s2!=0) begin//2
If (s1!=0) begin//3
If (m2! Begin//4=0)
If (m1!=0) begin s2=s2-1; End
Else if (s1!=0) begin s2 & lt;=9; S1 & lt; S1=1; End
Else if (m2! The begin s1=0) & lt;=5; M2 & lt;=m2-1; End
The else begin m2 & lt;=9; M1 & lt;=m1-1; End//3
End//2
End//1
End//0
End
End
//-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --



//-- -- -- -- -- -- -- -- -- -- -- --, stop time,
The clear:
The begin
S1 & lt;=0; S2 & lt;=0; M1 & lt;=0; M2 & lt;=0;
End
//-- -- -- -- -- -- -- -- -- -- -- -- pause, stop timing
Pause:
The begin
S1 & lt;=s1; S2 & lt;=s2; M1 & lt;=m1; M2 & lt;=m2;
End

Endcase
End

Endmodule




The simulation module:
` timescale ns/1 ps
//test for pause and count
The module test ();
Reg CLK, RST;
Reg sw;
Wire [3-0] m1, m2, s1, s2.
A stopwatch u1 (CLK, RST, m1, m2, s1, s2, sw);
Always # 5 CLK=~ CLK;
Initial
The begin
CLK=0;
RST=0;
# 10 RST=1;
Sw=3 'b001;//reset
# 200 sw=3 'b110;//timing begins
# 300 sw=3 'b111;//300 s after 7, suspend
# 1000 sw=3 'b110;//after 200
# 2000 sw=3 'b111;//suspended after 1000
# 5100 sw=3 'b001;
# 9000 sw=3 'b110;
End

endmodule