I ask you a great god, and recently contact ZYNQ 7 PCIE knowledge, data interaction for RC and EP is a little bit confused, I ask, EP side if you want to and the RC and data interaction, is not only need the data into the DDR and RC side to take; If the EP end accept is rc end directly into DDR and EP to read data from DDR, the EP does not need to participate in the PCIE bus scheduling, is that so? Other RC side development of naked run program will be of great difficulty, whether recommend way of development, what? RC side development information where to find? Hope can get everybody's help, thank you!