The for loop outside the intial block generates hardware (with genvar), but the for loop in intial block in verilog works like the software for loop right?

The intial block is ofcourse only for simulation purposes so the software for loop makes sense.

One example is here. The test bench from that example that displays the use of the for loops in discussion is shown below:

module fsm_test;

reg  clk, rst, inp;
wire outp;
reg[15:0] sequence;
integer i;

fsm dut( clk, rst, inp, outp);

initial
begin

   clk = 0;
        rst = 1;
        sequence = 16'b0101_0111_0111_0010;
   #5 rst = 0;

   for( i = 0; i <= 15; i = i   1)
   begin
      inp = sequence[i];
      #2 clk = 1;
      #2 clk = 0;
      $display("State = ", dut.state, " Input = ", inp, ", Output = ", outp);

   end
        test2;
end
task test2;
   for( i = 0; i <= 15; i = i   1)
   begin
      inp = $random % 2;
      #2 clk = 1;
      #2 clk = 0;
      $display("State = ", dut.state, " Input = ", inp, ", Output = ", outp);

   end
endtask


endmodule

CodePudding user response：

All code that you write in Verilog can be simulated (assuming no syntax or semantic errors). Only a subset of the code you write and simulate can be synthesized into hardware. The simulator has no knowledge of what subset will eventually be synthesized, the executional behavior is the same.

A simulator executes a procedural-for loop the same way it would in almost any software programming langauge in 3-steps

1. Initialize the loop variable.
2. Test the condition; if true, procedurally execute the loop body statements; if false, proceed to the statement following the for loop.
3. Increment the loop variable (or whatever needs to be done) at the end of the loop and go back to step 2.

A simulator unrolls a generate-for loop prior to execution. It simply replicates the code inside the loop replacing the loop variable with. different constant loop value for each replication of the loop. And the code inside a generate-for loop is not procedural statements; the code will be instances of structure that could be other always or initial blocks.

A synthesis tool never executes procedural code. From its perspective, there is no difference between a generate-for and a procedural-for; it unrolls both loops into a replications of the loop with a different constant loop value of each iteration of the loop.