Such as "ADC_out_Z & lt;=L_15 + L_14 + L_13 + L_12 + L_11 + L_10 + + L_8 L_9 + L_7 + L_6;"
At the same time dealing with ten data addition will cause the result is not correct, more than ten even more so, what reason is this?
CodePudding user response:
Are you sure they aren't in the test?Verilog C language, and it is used to describe the hardware circuit,
If you have more digits addition, recommend two together, into two DFF, may need to fit between can improve the circuit operating frequency,
CodePudding user response:
Two two together will be more complex, the timing requirements for five data addition, today I tried into many groups, the calculation result is normal, because the FPGA can't handle this multiple addition assignment at the same time, for example, for multiple addition, need to use the gate, there is no guarantee that the correct results?CodePudding user response:
Logic levels, timing is not satisfied,