The module dot_array_driver
(
The input CLK,
Input rst_n,
Input [3-0] sw1,
Input [3-0] sw2,
The output reg [away] colr,
The output reg [away] colg,
The output reg [away] row
);
Localparam s0=3 'd0, s1=3' d1, s2=3 'd2, s3=3 d3,
S4=3 'd4, s5=3 d5, s6=3' d6, s7=3 d7.
Reg [12:0] CNT;
Always @ (posedge CLK or negedge rst_n)
if(! Rst_n) CNT & lt;=1 'b0;
Else if (CNT & gt; D62499) CNT=16 '& lt;=1 'b0;
The else CNT & lt; CNT=+ 1 'b1;
Reg clk_800hz;
Always @ (posedge CLK or negedge rst_n)
if(! Rst_n) clk_800hz & lt;=1 'b0;
Else if (CNT==16 'd62499) clk_800hz & lt;=~ clk_800hz;
The else clk_800hz & lt;=clk_800hz;
Reg [63:0] mem [9:0];
Always begin
Mem [0]={8 '8' h00, h00, 8 '8' h00, h18, 8 '8' h18, h00, 8 '8' h00, h00};//0
Mem [1]={8 '8' h00, h00, 8 '8' h00, h00, 8 '8' h00, h00, 8 '8' h00, h00};//1
Mem [2]={8 '8' h00, h3c, 8 'h42, 8' h5a, 8 '8' h5a, h42, 8 '8' h3c, h00};//2
Mem [3]={8 '8' h36, h80, 8 '8' h99, h25, 8 '8' ha4, h99, 8 'h01-2, 8' h6c};//3 red
Mem [4]={8 '8' h00, h00, 8 '8' h00, h18, 8 '8' h18, h00, 8 '8' h00, h00};//4
Mem [5]={8 '8' h00, h00, 8 '8' h18, h24, 8 '8' h24, h18, 8 '8' h00, h00};//5
Mem [6]={8 '8' h00, h00, 8 '8' h00, h18, 8 '8' h18, h00, 8 '8' h00, h00};//6
Mem [7]={8 '8' h6c, h01-2, 8 '8' h99, ha4, 8 '8' h25, h99, 8 'h80, 8' h36};//7 green
Mem [8]={8 '8' h00, h00, 8 '8' h36, h49, 8 '8' h49, h49, 8 '8' h36, h00};//8
Mem [9]={8 '8' h00, h00, 8 'h06, 8' h49, 8 '8' h49, h29, 8 '8' h1E, h00};//9
End
Reg [2-0] state;
Always @ (posedge clk_800hz or negedge rst_n)
if(! Rst_n) begin state & lt;=s0; The row & lt; HFF=8 '; Colr=8 'HFF; Colr=8 'HFF; End
The else case (state)
S0: begin row & lt;=8 'b1111_1110; Colr=~ mem [sw1] [8] 56 + :; Colg=~ mem [sw2] [8] 56 + :; The state & lt;=s1; End
S1: the begin row & lt;=8 'b1111_1101; Colr=~ mem [sw1] [8] 48 + :; Colg=~ mem [sw2] [8] 56 + :; The state & lt;=s2; End
S2: the begin row & lt;=8 'b1111_1011; Colr=~ mem [sw1] [8] 40 + :; Colg=~ mem [sw2] [8] 56 + :; The state & lt;=s3; End
S3: begin row & lt;=8 'b1111_0111; Colr=~ mem [sw1] [8] 32 + :; Colg=~ mem [sw2] [8] 56 + :; The state & lt;=s4; End
S4: begin row & lt;=8 'b1110_1111; Colr=~ mem [sw1] [8] 24 + :; Colg=~ mem [sw2] [8] 56 + :; The state & lt;=s5; End
S5: begin row & lt;=8 'b1101_1111; Colr=~ mem [sw1] [8] 16 + :; Colg=~ mem [sw2] [8] 56 + :; The state & lt;=s6; End
S6: begin row & lt;=8 'b1011_1111; Colr=~ mem [sw1] [: 8 + 8]; Colg=~ mem [sw2] [8] 56 + :; The state & lt;=s7; End
S7: the begin row & lt;=8 'b0111_1111; Colr=~ mem [sw1] [8] 0 + :; Colg=~ mem [sw2] [8] 56 + :; The state & lt;=s0; End
Default: begin state & lt;=s0; The row & lt; HFF=8 '; Colr=8 'HFF; Colg=8 'HFF; End
Endcase
Endmodule
The module newyear
(the input CLK,
Input rst_n,
The output wire [away] row,
The output wire [away] colr,
The output wire [away] colg
);
Reg [12:0] CNT;
Always @ (posedge CLK)
if(! Rst_n) CNT & lt;=1 'b0;
Else if (CNT & gt; D12_499_999) CNT=24 '& lt;=1 'b0;
The else CNT & lt; CNT=+ 1 'b1;
Reg clk_4hz;
Always @ (posedge CLK)
if(! Rst_n) clk_4hz & lt;=1 'b0;
Else if (CNT==24 'd12_499_999) clk_4hz & lt;=~ clk_4hz;
The else clk_4hz & lt;=clk_4hz;
Reg [2-0] state;
Reg [3-0] sw1;
Reg [3-0] sw2;
Dot_array_driver driver (CLK, rst_n, sw1, sw2, colr, colg, row);
Always @ (posedge clk_4hz or negedge rst_n)
if(! Rst_n) begin state & lt;=0; End
The else case (state)
Zero: the begin sw1 & lt;=0; Sw2 & lt;=4; The state & lt;=1; End
1: the begin sw1 & lt;=1; Sw2 & lt;=5; The state & lt;=2; End
2: the begin sw1 & lt;=2; Sw2 & lt;=6; The state & lt;=3; End
3: the begin sw1 & lt;=3; Sw2 & lt;=7. The state & lt;=0; End
Default: begin state & lt;=0; End
Endcase
Endmodule
CodePudding user response:
I know that made a silly mistake