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The FPGA digital clock design problems

Time:09-26

Bosses give directions, just contact verilog language is a small white
Digital clock design requirements:
1. The basic timing and display
(2) dynamic scanning display (3) (1) shows 24 hours display format in 88-88-88
2. To set the current time (, minutes, seconds)

CodePudding user response:

refer to the original poster qq_45854178 response:
o bosses, just contact verilog language is a small white
Digital clock design requirements:
1. The basic timing and display
(2) dynamic scanning display (3) (1) shows 24 hours display format in 88-88-88
2. To set the current time (hours, minutes, seconds)

Can do for you, QQ2972880695
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