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Verilog beginners can't write the simulation file

Time:09-27

Bosses have any books or materials recommended self-study with simulation are less likely to be written

CodePudding user response:

CodePudding user response:

Eetop ramble on

CodePudding user response:

https://blog.csdn.net/k331922164/article/details/44626989

CodePudding user response:

Understand writing motivation file first, then, don't try to write complex, write the most simple

CodePudding user response:

To buy materials in this line

CodePudding user response:

You can try a simple design, such as adder, write a testbench
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