New reports, universal love, kneel down to worship first,
Project, the need to do a sampling rate of real-time acquisition, 3 g ADC sampling rate for 3 g, points the ABCD four channel output data (single channel frequency 750 m), and then going to use the FPGA, OK? Measures for the implementation of a specific point genuflect is begged

CodePudding user response:

You are the 3 g is too high, you confirm didn't make a mistake?

CodePudding user response:

reference 1st floor xuweiwei1860 response:

you this 3 g is too high, are you sure didn't make a mistake?

Mxt2003, domestic imitation AD083000, AD has run up, but the AD of the output clock and data FPGA side often misplaced or directly to receive less than,

CodePudding user response:

ADC12D1800
12 - Bit, Single 3.6 GSPS Ultra High -speed ADC

Using Xilinx FPGA faster then can

CodePudding user response:

At least also want to cyclone | | |

CodePudding user response:

With V - 7 series chips can solve this problem

CodePudding user response:

3 g frequency is very high, the AD of the output clock and data FPGA side often misplaced or directly to receive less than is likely to be caused by interference, PCB design good rf shielding measures must be taken,