Beginners VHDL, I know that as long as it is good to add 15.16 a 00, but do not know how to add. Whatever I put my "input1: std_logic_vector (downto 15 0);" In any place error
This is the code
The library ieee.
Use the ieee. Std_logic_1164. All;
The entity tristate_buffer16 is
The port (input: in std_logic_vector downto 0 (13);
Enable: in std_logic;
Output: the out std_logic_vector (downto 15 0));
End tristate_buffer16;
Architecture behav of tristate_buffer16 is
The begin
The process (input, enable)
The begin
If (enable='1') then
Input1 & lt; Downto 0==(1 & gt; '0') & amp; The input;
The output & lt;=input1;
The else
The output & lt;="ZZZZZZZZZZZZZZZZ";
end if;
End the process.
End behav.

CodePudding user response:

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- Company:
- Engineer:
-
- the Create Date: 11:41:27 09/09/2019
- the Design Name:
- the Module Name: Tribuf - Behavioral
- the Project Name:
-- Target Devices:
- the Tool versions:
Description:
-
- Dependencies:
-
Revision:
- Revision 0.01 File Created
- Additional Comments:
-
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The library IEEE.
Use the IEEE. STD_LOGIC_1164. ALL;
Use the IEEE. STD_LOGIC_ARITH. ALL;
Use the IEEE. STD_LOGIC_UNSIGNED. ALL;

- Uncomment the following library declaration if instantiating
- any Xilinx primitives in this code.
- library UNISIM;
- use UNISIM. VComponents. All;

The entity Tribuf is
Port (IOin: in STD_LOGIC_VECTOR (downto 15 0);
IOen: in STD_LOGIC;
IOout: out STD_LOGIC_VECTOR (downto 15 0));
End Tribuf;

Architecture Behavioral of Tribuf is
The begin
IOout & lt;='1'=IOin the when IOen else "ZZZZZZZZZZZZZZZZ";
End Behavioral;