The code is as follows:
The LIBRARY IEEE.
USE the IEEE. STD_LOGIC_1164. ALL;
USE the IEEE. STD_LOGIC_ARITH. ALL;
USE the IEEE. STD_LOGIC_UNSIGNED. ALL;
The ENTITY regfile IS
The PORT (
CLK: IN STD_LOGIC; - the clock
Reset: IN STD_LOGIC;
MA: IN STD_LOGIC_VECTOR DOWNTO 0 (4);
MB: IN STD_LOGIC_VECTOR DOWNTO 0 (4);
WN: IN STD_LOGIC_VECTOR (31 DOWNTO 0); - determine the address as ma and MB
D: IN STD_LOGIC_VECTOR (31 DOWNTO 0); - data
QA: OUT STD_LOGIC_VECTOR (31 DOWNTO 0); - reg (ma)
QB: OUT STD_LOGIC_VECTOR (31 DOWNTO 0) - reg (MB)
);
END regfile;
ARCHITECTURE regfile_body OF regfile IS
31 DOWNTO TYPE my_array IS ARRAY (0) OF STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL reg: my_array;
The BEGIN
The PROCESS (CLK, RESET, MA, MB, WN, D)
The BEGIN
IF the RESET='0' THEN
For I in 0 to 31 loop
Reg (I) & lt; X="00000000";
End loop;
ElsIF CLK 'EVENT AND CLK=' 0 'THEN
IF (WN (31 DOWNTO 30)="00") THEN
IF (WN (29 DOWNTO 26)="0000") THEN type -- - registers ALU instructions
REG (CONV_INTEGER (MA)) & lt;=D;
The ELSE - register - immediately for the ALU instructions
REG (CONV_INTEGER (MB)) & lt;=D;
END the IF;
END the IF;
END the IF;
END the PROCESS.
QA & lt;=REG (CONV_INTEGER (MA));
QB & lt;=REG (CONV_INTEGER (MB));
END regfile_body;