This is the original code that is


This is a simulation program

Will appear the following error
ERROR: 17-39 [Common] 'launch_simulation failed due to earlier errors.

I don't think my code should have write wrong, went to the game spirit thought's website to see it was useless to answer this question, asking god taught this do??
Thank you very much!!!!!

CodePudding user response:

Error path open elaborate. The log to see
Vivado Simulator 2018.3
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: E:/vivado/vivado/2018.3/bin/unwrapped/win64. O/xelab. Exe - wto a6f9ffc099a643df897540ea2176c83d - incr - debug typical - relax - mt xil_defaultlib - 2 - L L unisims_ver -l unimacro_ver -l secureip - the snapshot tb_gates2_behav xil_defaultlib. Tb_gates2 xil_defaultlib. GLBL - log elaborate. The log
Using 2 slave threads.
Starting the static elaboration
ERROR: 10-3236] [VRFC concurrent the assignment to a non -.net 'b' is not permitted [E:/vivado/gate2/4 input. SRCS/sim_1/new/tb_gates2. V: 30]
ERROR: [VRFC 10-3595] non -.net variable always be connected to inout port 'b' [E:/vivado/gate2/4 input. SRCS/sim_1/new/tb_gates2. V: 30]
ERROR: 43-3322] [XSIM Static elaboration of top level Verilog design unit (s) in the library work failed.

Know about 30 lines are wrong, that could you tell me where is wrong?

CodePudding user response:

Inout b? Double port? Do not use the
To input!

CodePudding user response:

General simulation code is wrong, such as the format is wrong, the signal is not defined, grammatical errors, such as by observation of Tcl Console window ERRO where the number of rows, corresponding modification error! Or can be in the project file & gt; The simulation file & gt; The simulation file. Sim> The compile. The log file to check the compiler error, the experience I have just found in the baidu, I met the original poster is error, and then use these methods successfully simulated

CodePudding user response:

Has told you tip: signal b if defined as inout, cannot use reg, into a type wire should be good

CodePudding user response:

You this is inout b; This is wrong, you should input the input b

CodePudding user response:

Connect a upstairs: inout b is wrong, to the input b