Recently used HMC767 phase-locked loop, 50 m reference frequency, output 8.55 G, all internal configuration register, speaking, reading and writing, and is not locked, solving
Register configuration is as follows:
REG 1 2
REG 2 1
REG 5 50 f1cd
REG d3f 6 1
REG 7 304865
REG 8 16 FFF
REG 9 3264
REG 1 B e061
REG E 1
REG F 81
REG 3 AB

Schematic diagram below



Warrior, please comment, thank you!

CodePudding user response:

Lower point frequency have a try

CodePudding user response:

Thank you for your guidance!
Under the consultation on the BBS of ADI, get inspired, HMC767 is now locked, but the output frequency has been 8.03 GHZ, no matter how to change all the same, a wave of open something

CodePudding user response:

You did not give out the loop filter, so I can't see the loop parameters, I can only assume you loop parameters is right,

According to your register, FRAC is you don't have to register 4

According to your statement, please try configuration:

REG 3 0 x2a
4 0 xc00000 REG

CodePudding user response:

Thank you for your guidance!
We use a integer model, now the problem is to configure the registers, locked, output has always been about 8 GHZ, no matter how to modify the N frequency division, the output is the same;

CodePudding user response:

Attach the external loop filter circuit

CodePudding user response:

1. I've been meaning to ask you, you are reading lock instructions (LockDetect) judge locked? Is it possible to lock because you must be at least 8.45 G, if 8 G, lock indicator can't lock,

2. The loop active ah,,, if it is possible to use passive to adjust, if bad phase manic besides,


The inside of the parameters is an ideal value, buy approximation can, only need to pay attention to is R2 don't smaller than this value, the first adjustable direct welding a few bigger, you can put the R2 from 510 can be, it's so easy to lock, phase noise will be worse, of course, you can successfully locked you debug index can slowly again,

About the parameters of the loop, you download the ADI SIMPLL simulation,

This is mark phase-locked loop, as far as possible use the decimal, the manic phase of the help,

CodePudding user response:

I just found out that you REF 24 feet, the front have a PI attenuator, what is this? Why not just go in?

CodePudding user response:

Thanks for guidance!
1. The lock is through reading a Reg12 register, and LD signals to judge, shows the lock both ways;
2. We've been measured active passive, the effect is not big, the other circuit is refer to the demo board, the position of the R2 also altered, no effect;
3. The REF is because we are in front of the clock crystals after the output amplifier, increase PI circuit is an attenuation, and the meaning of isolation;

Please look at the register now are there any questions, and total output for 8 GHZ, is what circumstance, thank you!
REG 1 2
REG 2 1
REG 5 1
REG c3e 6 1
REG 7 204865
REG 8 36 FFF
REG 9 803 FFF
REG 1 B f069
REG E 1
REG F 81
REG 3 2 d

CodePudding user response:

Register looks no problem,
Can also be simple point, because in the integer mode, automatic ignore trig no buffer, only need to pay attention to the
"Disabled" Charge Pump Offset Reg 09 [then]=00
And then there are the Reg 06 [then]=1
Then it is Reg 3=AB

SEED I think should not set relationship,

I don't know if or 8 g, can only help you so much, uh,

CodePudding user response:

Ok, thank you very much, we will study the

CodePudding user response:

Warrior, we HMC767 encountered new problems, under the guidance of help please:
1. The stable output frequency cut right now, but from reg 12 and LD pin didn't lock signal;
2. When the locking signal detected, the output frequency is not correct, and cannot be modified;
3. We in the SPI interface SCK increased pulldown resistor, can have a correct output, if cancel the no output;

These questions is what reason, please?

CodePudding user response:

Bad feeling don't use the active filter, voltage control, temperature influence is bigger,